公开(公告)号：US10977036B2

公开(公告)日：2021-04-13

申请号：US16336884

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Patrick Lu ,  Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Martin P. Dimitrov

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/0862 ,  G06F9/38

Abstract: An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.

公开(公告)号：US20190220424A1

公开(公告)日：2019-07-18

申请号：US15870749

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Thomas Willhalm ,  Karthik Kumar ,  Daniel Rivas Barragan ,  Patrick Lu

IPC: G06F13/16 ,  G06F12/0831 ,  G06F13/24 ,  G06F12/0837

CPC classification number: G06F13/1663 ,  G06F12/0831 ,  G06F12/0837 ,  G06F13/24 ,  G06F2212/621

Abstract: Techniques and mechanisms for providing a shared memory which spans an interconnect fabric coupled between compute nodes. In an embodiment, a field-programmable gate array (FPGA) of a first compute node requests access to a memory resource of another compute node, where the memory resource is registered as part of the shared memory. In a response to the request, the first FPGA receives data from a fabric interface which couples the first compute node to an interconnect fabric. Circuitry of the first FPGA performs an operation, based on the data, independent of any requirement that the data first be stored to a shared memory location which is at the first compute node. In another embodiment, the fabric interface includes a cache agent to provide cache data and to provide cache coherency with one or more other compute nodes.

公开(公告)号：US20190004910A1

公开(公告)日：2019-01-03

申请号：US15635245

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Daniel Rivas Barragan ,  Patrick Lu

IPC: G06F11/20 ,  H04L29/06

Abstract: A network controller, including: a processor; and a resource permission engine to: provision a composite node including a processor and a first disaggregated compute resource (DCR) remote from the processor, the first DCR to access a target resource; determine that the first DCR has failed; provision a second DCR for the composite node, the second DCR to access the target resource; and instruct the target resource to revoke a permission for the first DCR and grant the permission to the second DCR.

公开(公告)号：US12235761B2

公开(公告)日：2025-02-25

申请号：US16514226

申请日：2019-07-17

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Priya Autee ,  Abhishek Khade ,  Patrick Lu ,  Edwin Verplanke ,  Vivekananthan Sanjeepan

IPC: G06F12/0802

Abstract: Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.

公开(公告)号：US11886884B2

公开(公告)日：2024-01-30

申请号：US16680907

申请日：2019-11-12

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Binh Pham ,  Patrick Lu ,  Jared Warner Stark, IV

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/3004 ,  G06F9/30058

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

公开(公告)号：US10558574B2

公开(公告)日：2020-02-11

申请号：US15992557

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： Abhishek Khade ,  Patrick Lu ,  Francesc Guim Bernat

IPC: G06F12/08 ,  G06F12/0846

Abstract: There is disclosed in one example a computing apparatus, including: a cache; a caching agent (CA); an integrated input/output (IIO) block to provide a cache coherent interface to a peripheral device at a first speed; a core configured to poll an address within the cache via the CA, wherein the address is to receive incoming data from the peripheral device via the IIO, and wherein the core is capable of polling the address at a second speed substantially greater than the first speed; and a hardware uncore agent configured to: identify a collision between the core and the IIO including determining that the core is polling the address at a rate that is determined to interfere with access to the address by the IIO; and throttle the core's access to the address.

公开(公告)号：US10949313B2

公开(公告)日：2021-03-16

申请号：US15635245

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Susanne M. Balle ,  Daniel Rivas Barragan ,  Patrick Lu

IPC: G06F11/00 ,  G06F11/20 ,  G06F21/44 ,  G06F21/62 ,  H04L29/08 ,  G06F21/71 ,  H04L29/06

Abstract: A network controller, including: a processor; and a resource permission engine to: provision a composite node including a processor and a first disaggregated compute resource (DCR) remote from the processor, the first DCR to access a target resource; determine that the first DCR has failed; provision a second DCR for the composite node, the second DCR to access the target resource; and instruct the target resource to revoke a permission for the first DCR and grant the permission to the second DCR.

公开(公告)号：US10318417B2

公开(公告)日：2019-06-11

申请号：US15476866

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Patrick Lu ,  Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm

IPC: G06F12/08 ,  G06F12/06 ,  G06F12/0873 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/02 ,  G06F13/16 ,  G06F13/42

Abstract: Persistent caching of memory-side cache content for devices, systems, and methods are disclosed and discussed. In a system including both a volatile memory (VM) and a nonvolatile memory (NVM), both mapped to the system address space, software applications directly access the NVM, and a portion of the VM is used as a memory-side cache (MSC) for the NVM. When power is lost, at least a portion of the MSC cache contents is copied to a storage region in the NVM, which is restored to the MSC upon system reboot.

公开(公告)号：US20180157591A1

公开(公告)日：2018-06-07

申请号：US15369594

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Ren Wang ,  Namakkal N. Venkatesan ,  Patrick Lu

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1016 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/6028

Abstract: Embodiments provide for a processor comprising a cache, a prefetcher to select information according to a prefetcher algorithm and to send the selected information to the cache, and a prefetch tuning buffer including tuning state for the set of candidate prefetcher algorithms, wherein the prefetcher is to adjust operation of the prefetcher algorithm based on the tuning state.

公开(公告)号：US20200081718A1

公开(公告)日：2020-03-12

申请号：US16680907

申请日：2019-11-12

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Binh Pham ,  Patrick Lu ,  Jared Warner Stark, IV

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.