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    Apparatuses, methods, and systems to accelerate store processing
    3.
    发明授权
    Apparatuses, methods, and systems to accelerate store processing 有权

    公开(公告)号：US10754782B1

    公开(公告)日：2020-08-25

    申请号：US16370893

    申请日：2019-03-30

    申请人： Intel Corporation

    发明人： Binh Pham ,  Chen Dan

    IPC分类号： G06F12/00 ,  G06F12/0875 ,  G06F12/0831 ,  G06F9/54 ,  G06F9/30 ,  G06F16/901 ,  G06F12/12

    摘要： Systems, methods, and apparatuses relating to circuitry to accelerate store processing are described. In one embodiment, a processor includes a (e.g., L1) cache, a fill buffer, a store buffer, and a cache controller to allocate a first entry of a plurality of entries in the fill buffer to store a first storage request when the first storage request misses in the cache, send a first request for ownership to another cache corresponding to the first storage request, detect a hit in the cache for a second storage request, update a globally observable buffer to indicate the first entry in the fill buffer for the first storage request is earlier in program order than the second storage request in the store buffer, allocate, before the second storage request is removed from the store buffer, a second entry of the plurality of entries in the fill buffer to store the third storage request when the third storage request misses in the cache, send a second request for ownership to another cache corresponding to the third storage request, and update the globally observable buffer to indicate the second entry in the fill buffer for the third storage request is later in program order than the second storage request in the store buffer.

    Programmable address range engine for larger region sizes
    5.
    发明授权
    Programmable address range engine for larger region sizes 有权

    公开(公告)号：US11989135B2

    公开(公告)日：2024-05-21

    申请号：US16786815

    申请日：2020-02-10

    申请人： Intel Corporation

    发明人： Farah E. Fargo ,  Mitchell Diamond ,  David Keppel ,  Samantika S. Sury ,  Binh Pham ,  Shobha Vissapragada

    IPC分类号： G06F12/10 ,  G06F12/1027

    CPC分类号： G06F12/1027 ,  G06F2212/657

    摘要： Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.