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公开(公告)号：US20240329938A1
公开(公告)日：2024-10-03
申请号：US18607024
申请日：2024-03-15
申请人： Intel Corporation
发明人： Menachem Adelman , Robert Valentine , Barukh Ziv , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Mark J. Charney , Christopher J. Hughes , Alexander F. Heinecke , Evangelos Georganas , Binh Pham
CPC分类号： G06F7/78 , G06F9/3001 , G06F9/3016 , G06F17/16
摘要： Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.
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2.发明授权公开(公告)号：US12056601B2
公开(公告)日：2024-08-06
申请号：US16830733
申请日：2020-03-26
发明人： Hieu Van Tran , Steven Lemke , Vipin Tiwari , Nhan Do , Mark Reiten
IPC分类号： G06F1/03 , G06F7/78 , G06F11/16 , G06F17/16 , G06N3/065 , G11C11/54 , G11C11/56 , G11C13/00 , G11C29/44
CPC分类号： G06N3/065 , G06F1/03 , G06F7/78 , G06F11/1666 , G06F17/16 , G11C11/54 , G11C11/5635 , G11C13/0021 , G11C29/44
摘要： Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.
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3.发明公开公开(公告)号：US20240192925A1
公开(公告)日：2024-06-13
申请号：US18325836
申请日：2023-05-30
申请人： SK hynix Inc.
发明人： Gi Moon HONG , Dae Han KWON
IPC分类号： G06F7/78 , G11C11/408 , G11C11/4091 , G11C11/4096
CPC分类号： G06F7/78 , G11C11/4085 , G11C11/4091 , G11C11/4096
摘要： A memory core includes a first signal line; a second signal line; a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element; and a switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and a second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor.
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公开(公告)号：US20240152799A1
公开(公告)日：2024-05-09
申请号：US18051364
申请日：2022-10-31
申请人： ADOBE INC.
发明人： Sudhanshu Chanpuriya , Ryan A. Rossi , Nedim Lipka , Anup Bandigadi Rao , Tung Mai , Zhao Song
摘要： Systems and methods for data augmentation are described. Embodiments of the present disclosure receive a dataset that includes a plurality of nodes and a plurality of edges, wherein each of the plurality of edges connects two of the plurality of nodes; compute a first nonnegative matrix representing a homophilous cluster affinity; compute a second nonnegative matrix representing a heterophilous cluster affinity; compute a probability of an additional edge based on the dataset using a machine learning model that represents a homophilous cluster and a heterophilous cluster based on the first nonnegative matrix and the second nonnegative matrix; and generate an augmented dataset including the plurality of nodes, the plurality of edges, and the additional edge.
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公开(公告)号：US20240152332A1
公开(公告)日：2024-05-09
申请号：US18500210
申请日：2023-11-02
申请人： Robert Bosch GmbH
CPC分类号： G06F7/78 , G06F7/49942
摘要： A method for approximatively determining at least one scalar product of at least one input vector with a weight vector. Input components of the input vector and weight components of the weight vector are present in binary form. At least one matrix circuit is used, wherein the memory cells are programmed according to bits of the weight components. Bits with the same significance of at least a portion of the weight components are respectively programmed in memory cells of the same column. For each of one or more subsets of the input components, a bit sum determination is carried out. To a corresponding subset of the row lines, voltages are applied according to bits with the same significance of the respective subset of the input components and a limited bit sum is determined as the output value of the respective analog-to-digital converter.
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公开(公告)号：US20240134931A1
公开(公告)日：2024-04-25
申请号：US18076407
申请日：2022-12-07
申请人： NEUCHIPS CORPORATION
发明人： Chiung-Liang Lin , YuShan Ruan , Huan Jan Chou
CPC分类号： G06F17/16 , G06F7/50 , G06F7/523 , G06F7/5443 , G06F7/78
摘要： A matrix computing device and an operation method for the matrix computing device are provided. The matrix computing device includes a storage unit, a control circuit, and a computing circuit. The storage unit includes a weight matrix. The control circuit re-orders an arrangement order of weights in the weight matrix according to a shape of an output matrix to determine a weight readout order of the weights. The computing circuit receives the weights based on the weight readout order, and performs a matrix computation on the weights and an input matrix to generate a computing matrix. The control circuit performs a reshape transformation on the computing matrix to generate the output matrix, and writes the output matrix to the storage unit.
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公开(公告)号：US20240104342A1
公开(公告)日：2024-03-28
申请号：US18521425
申请日：2023-11-28
发明人： Xinlin LI , Vahid PARTOVI NIA
CPC分类号： G06N3/04 , G06F7/49942 , G06F7/78
摘要： Methods, systems and computer readable media using hardware-efficient bit-shift operations for computing the output of a low-bit neural network layer. A dense shift inner product operator (or dense shift IPO) using bit shifting in place of multiplication replaces the inner product operator that is conventionally used to compute the output of a neural network layer. Dense shift neural networks may have weights encoded using a low-bit dense shift encoding. A dedicated neural network accelerator is designed to compute the output of a dense shift neural network layer using dense shift IPOs. A Sign-Sparse-Shift (S3) training technique trains a low-bit neural network using dense shift IPOs or other bit shift operations in computing its outputs.
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公开(公告)号：US11928443B2
公开(公告)日：2024-03-12
申请号：US16721458
申请日：2019-12-19
申请人： Intel Corporation
发明人： Hong Shan Neoh
IPC分类号： G06F7/78
CPC分类号： G06F7/78
摘要： A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing elements in first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading elements in first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.
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9.发明授权公开(公告)号：US11847556B2
公开(公告)日：2023-12-19
申请号：US17875281
申请日：2022-07-27
发明人： Hieu Van Tran , Steven Lemke , Vipin Tiwari , Nhan Do , Mark Reiten
IPC分类号： G06N3/065 , G11C11/54 , G06F1/03 , G06F17/16 , G11C11/56 , G06F11/16 , G11C13/00 , G11C29/44 , G06F7/78
CPC分类号： G06N3/065 , G06F1/03 , G06F7/78 , G06F11/1666 , G06F17/16 , G11C11/54 , G11C11/5635 , G11C13/0021 , G11C29/44
摘要： Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.
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公开(公告)号：US20230306249A1
公开(公告)日：2023-09-28
申请号：US18134726
申请日：2023-04-14
发明人： Jeffrey T Huynh , Vignesh Vivekraja
CPC分类号： G06N3/063 , G06F7/50 , G06F7/523 , G06F7/5443 , G06F7/78 , G06F9/5027 , G06F17/153
摘要： In one example, a neural network accelerator can execute a set of instructions to: load a first weight data element from a memory into a systolic array, the first weight data element having first coordinates; extract, from the instructions, information indicating a first subset of input data elements to be obtained from the memory, the first subset being based on a stride of a transposed convolution operation and second coordinates of first weight data element in a rotated array of weight data elements; based on the information, obtain the first subset of input data elements from the memory; load the first subset of input data elements into the systolic array; and control the systolic array to perform first computations based on the first weight data element and the first subset of input data elements to generate output data elements of an array of output data elements.
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