公开(公告)号：US20180350761A1

公开(公告)日：2018-12-06

申请号：US16101114

申请日：2018-08-10

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Franziska Haering ,  Hans-Joachim Schulze ,  Bernhard Weidgans

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L24/05 ,  H01L21/76843 ,  H01L21/76858 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/03 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03848 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01074

摘要： A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.

公开(公告)号：US09887170B2

公开(公告)日：2018-02-06

申请号：US15592941

申请日：2017-05-11

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC分类号： H01L23/52 ,  H01L23/00

CPC分类号： H01L24/06 ,  H01L21/0273 ,  H01L21/76864 ,  H01L21/76865 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/03462 ,  H01L2224/05087 ,  H01L2224/05093 ,  H01L2224/05098 ,  H01L2224/05147 ,  H01L2224/0603 ,  H01L2224/065 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45176 ,  H01L2224/45181 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48484 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/1306 ,  H01L2924/35121 ,  H01L2924/00014

摘要： A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

公开(公告)号：US09780053B2

公开(公告)日：2017-10-03

申请号：US14941633

申请日：2015-11-15

申请人： Infineon Technologies AG

发明人： Magdalena Hoier ,  Peter Scherl ,  Manfred Schneegans

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/02

CPC分类号： H01L24/05 ,  H01L21/02697 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/03502 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05015 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0518 ,  H01L2224/05557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/0568 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4845 ,  H01L2224/48453 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/85365 ,  H01L2924/00014

摘要： Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.

公开(公告)号：US09640419B2

公开(公告)日：2017-05-02

申请号：US14451043

申请日：2014-08-04

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Martin Mischitz ,  Michael Roesner ,  Michael Pinczolits

IPC分类号： H01L21/683 ,  H01L21/02 ,  H01L23/00 ,  H01L23/495

CPC分类号： H01L21/6836 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/49551 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/28 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03602 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

摘要： In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier.

公开(公告)号：US20160260658A1

公开(公告)日：2016-09-08

申请号：US15155271

申请日：2016-05-16

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Andreas Meiser ,  Martin Mischitz ,  Michael Roesner ,  Michael Pinczolits

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/528 ,  H01L21/48 ,  H01L21/78

CPC分类号： H01L23/49562 ,  H01L21/4807 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/49 ,  H01L24/94 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03505 ,  H01L2224/03602 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/0603 ,  H01L2224/08245 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0532 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

摘要： A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

摘要翻译： 一种用于形成半导体器件的方法包括在具有第一侧和第二侧的半导体衬底中形成器件区域。 器件区域邻近第一侧形成。 该方法还包括在半导体衬底的第一侧上形成晶种层，并在种子层上形成图案化的抗蚀剂层。 在图案化的抗蚀剂层内的种子层上形成接触焊盘。 该方法还包括在形成接触焊盘之后去除图案化的抗蚀剂层，以暴露图案化抗蚀剂层下面的种子层的一部分，以及在种子层的暴露部分上形成保护层。

公开(公告)号：US09368436B2

公开(公告)日：2016-06-14

申请号：US14614119

申请日：2015-02-04

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Andreas Meiser ,  Martin Mischitz ,  Michael Roesner ,  Michael Pinczolits

IPC分类号： H01L21/78 ,  H01L23/528 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49562 ,  H01L21/4807 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/49 ,  H01L24/94 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03505 ,  H01L2224/03602 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/0603 ,  H01L2224/08245 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0532 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

摘要： A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

摘要翻译： 一种用于形成半导体器件的方法包括在具有第一侧和第二侧的半导体衬底中形成器件区域。 器件区域邻近第一侧形成。 该方法还包括在半导体衬底的第一侧上形成晶种层，并在种子层上形成图案化的抗蚀剂层。 在图案化的抗蚀剂层内的种子层上形成接触焊盘。 该方法还包括在形成接触焊盘之后去除图案化的抗蚀剂层，以暴露图案化抗蚀剂层下面的种子层的一部分，以及在种子层的暴露部分上形成保护层。

公开(公告)号：US20140327053A1

公开(公告)日：2014-11-06

申请号：US13886305

申请日：2013-05-03

申请人： INFINEON TECHNOLOGIES AG

发明人： Markus Zundel ,  Manfred Schneegans

IPC分类号： H01L29/04 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L21/823487 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device includes a trench transistor cell array in a silicon semiconductor body with a first main surface and a second main surface opposite to the first main surface. A main lateral face of the semiconductor body between the first main surface and the second main surface has a first length along a first lateral direction parallel to the first and second main surfaces. The first length is equal or greater than lengths of other lateral faces of the semiconductor body. The trench transistor cell array includes predominantly linear gate trench portions. At least 50% of the linear gate trench portions extend along a second lateral direction or perpendicular to the second lateral direction. An angle between the first and second lateral directions is in a range of 45°±15°.

摘要翻译： 半导体器件包括硅半导体本体中的沟槽晶体管单元阵列，其具有与第一主表面相对的第一主表面和第二主表面。 第一主表面和第二主表面之间的半导体本体的主侧面具有沿着平行于第一和第二主表面的第一横向方向的第一长度。 第一长度等于或大于半导体本体的其它侧面的长度。 沟槽晶体管单元阵列主要包括线性栅极沟槽部分。 至少50％的线性栅极沟槽部分沿着第二横向方向或垂直于第二横向方向延伸。 第一和第二横向之间的角度在45°±15°的范围内。

公开(公告)号：US11424201B2

公开(公告)日：2022-08-23

申请号：US16012341

申请日：2018-06-19

申请人： Infineon Technologies AG

发明人： Michael Rogalli ,  Johann Gatterbauer ,  Wolfgang Lehnert ,  Kurt Matoy ,  Evelyn Napetschnig ,  Manfred Schneegans ,  Bernhard Weidgans

IPC分类号： H01L23/00

摘要： A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.

公开(公告)号：US20180366427A1

公开(公告)日：2018-12-20

申请号：US16012341

申请日：2018-06-19

申请人： Infineon Technologies AG

发明人： Michael Rogalli ,  Johann Gatterbauer ,  Wolfgang Lehnert ,  Kurt Matoy ,  Evelyn Napetschnig ,  Manfred Schneegans ,  Bernhard Weidgans

IPC分类号： H01L23/00

摘要： A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.

公开(公告)号：US09209080B2

公开(公告)日：2015-12-08

申请号：US13715922

申请日：2012-12-14

申请人： Infineon Technologies AG

发明人： Manfred Schneegans ,  Bernhard Weidgans ,  Franco Mariani ,  Alexander Heinrich

IPC分类号： H01L21/00 ,  H01L21/78 ,  H01L29/45 ,  H01L23/367

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L23/3677 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/0657 ,  H01L29/45 ,  H01L2221/68327 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83191 ,  H01L2224/83365 ,  H01L2224/8382 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

摘要翻译： 半导体器件包括具有第一主面和第二主面的半导体芯片。 第二主面是半导体芯片的背面。 第二主面包括第一区域和第二区域。 第二区域是第二主面的周边区域，第一区域的高度和第二区域的高度不同。 第一区域可以用金属填充，并且可以被平坦化到与第二区域相同的水平。