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1.发明申请公开(公告)号：US20190103342A1
公开(公告)日：2019-04-04
申请号：US15724920
申请日：2017-10-04
发明人： Christian NEUGIRG , Peter Scherl
IPC分类号： H01L23/495 , H01L21/48 , H01L25/18 , H01L25/00
摘要： A semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.
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公开(公告)号：US20150124420A1
公开(公告)日：2015-05-07
申请号：US14071296
申请日：2013-11-04
CPC分类号： H05K1/11 , H01L24/45 , H01L24/46 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/45015 , H01L2224/45028 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45184 , H01L2224/4554 , H01L2224/48091 , H01L2224/48092 , H01L2224/48137 , H01L2224/48227 , H01L2224/48465 , H01L2224/48507 , H01L2224/48511 , H01L2224/85 , H01L2224/85181 , H01L2224/85205 , H01L2224/85207 , H01L2924/00014 , H01L2924/13055 , H01L2924/181 , H05K1/111 , H05K1/14 , H05K3/32 , H05K3/36 , H05K3/4015 , H05K2201/04 , H05K2203/0285 , Y10T29/49126 , H01L2924/00 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/00012 , H01L2224/48247 , H01L2224/43 , H01L2224/85399 , H01L2224/05599
摘要： An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.
摘要翻译： 电子器件可以包括半导体元件和将半导体元件连接到衬底的引线键合。 使用编织的接合线可以改善引线接合的机械和电学性质。 此外，可能会有成本效益。 编织接合线可用于任何电子设备中，例如功率器件或集成逻辑器件中。
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公开(公告)号：US20130075478A1
公开(公告)日：2013-03-28
申请号：US13626932
申请日：2012-09-26
发明人： Peter Scherl , Frank Pueschner , Juergen Hoegerl
IPC分类号： G06K19/067 , H05K13/00
CPC分类号： G06K19/025 , G06K19/07749
摘要： In various embodiments, a cover structure for a personal identification document is provided. The cover structure may include a cover formed as a single layer; a chip module; the cover having a recess for completely receiving the chip module; and an antenna that is connected to the chip module.
摘要翻译： 在各种实施例中，提供了用于个人识别文件的盖结构。 盖结构可以包括形成为单层的盖; 芯片模块; 所述盖具有用于完全接收所述芯片模块的凹部; 以及连接到芯片模块的天线。
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公开(公告)号：US20230223312A1
公开(公告)日：2023-07-13
申请号：US17572858
申请日：2022-01-11
发明人： Christian Neugirg , Adrian Lis , Peter Scherl , Ewald Guenther
IPC分类号： H01L23/367 , H01L23/498 , H01L23/00 , H01L23/31
CPC分类号： H01L23/367 , H01L23/49844 , H01L24/04 , H01L23/3171 , H01L23/3121 , H01L24/48 , H01L2224/48177 , H01L2224/04042
摘要： A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.
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公开(公告)号：US11652084B2
公开(公告)日：2023-05-16
申请号：US17078460
申请日：2020-10-23
发明人： Thorsten Meyer , Gerald Ofner , Stephan Bradl , Stefan Miethaner , Alexander Heinrich , Horst Theuss , Peter Scherl
IPC分类号： H01L23/00 , H01L23/495 , H01L23/31 , H01L21/677 , H01L21/56 , H01L21/67 , H01L21/48 , H01L21/78
CPC分类号： H01L24/96 , H01L21/4825 , H01L21/4839 , H01L21/561 , H01L21/677 , H01L21/67011 , H01L21/67703 , H01L21/78 , H01L23/3114 , H01L23/4952 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/97 , H01L21/565 , H01L21/568 , H01L23/3107 , H01L24/83 , H01L24/85 , H01L2224/0603 , H01L2224/291 , H01L2224/32245 , H01L2224/48247 , H01L2224/49111 , H01L2224/73265 , H01L2224/83005 , H01L2224/8384 , H01L2224/85005 , H01L2224/92247 , H01L2224/97 , H01L2924/181 , H01L2224/8384 , H01L2924/00014 , H01L2224/97 , H01L2224/83 , H01L2224/97 , H01L2224/85 , H01L2224/291 , H01L2924/014 , H01L2924/181 , H01L2924/00012 , H01L2224/73265 , H01L2224/32245 , H01L2224/48247 , H01L2924/00 , H01L2224/92247 , H01L2224/73265 , H01L2224/32245 , H01L2224/48247 , H01L2924/00
摘要： A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.
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公开(公告)号：US09633303B2
公开(公告)日：2017-04-25
申请号：US14215229
申请日：2014-03-17
发明人： Frank Pueschner , Juergen Hoegerl , Peter Scherl
IPC分类号： G06K19/06 , G06K19/077
CPC分类号： G06K19/07756 , G06K19/07745 , G06K19/07749 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/181 , Y10T29/49018 , H01L2924/00012 , H01L2924/00
摘要： In various embodiments, a smart card module arrangement is provided. The smart card module arrangement includes a carrier, in which a depression is formed, a smart card module, which is arranged in the depression, and a smart card antenna. The smart card antenna can be coupled to the smart card module in a contactless manner.
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公开(公告)号：US20140091450A1
公开(公告)日：2014-04-03
申请号：US14035579
申请日：2013-09-24
发明人： Frank Pueschner , Juergen Hoegerl , Peter Scherl , Thomas Spoettl
IPC分类号： H01L23/538
CPC分类号： H01L23/5388 , H01L23/49855 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/18161 , H01L2924/00012
摘要： A semiconductor housing includes a front side with a semiconductor chip and a first metallization on a substrate, and a rear side with a second metallization. The rear side is situated opposite the front side of the semiconductor housing. The semiconductor housing further includes a first compensation layer applied on the front side of the semiconductor housing.
摘要翻译： 半导体外壳包括具有半导体芯片的前侧和在基板上的第一金属化，以及具有第二金属化的后侧。 后侧与半导体外壳的前侧相对。 半导体外壳还包括施加在半导体外壳的前侧的第一补偿层。
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8.发明公开公开(公告)号：US20230245968A1
公开(公告)日：2023-08-03
申请号：US17579727
申请日：2022-01-20
发明人： Peter Scherl , Adrian Lis , Christian Neugirg
IPC分类号： H01L23/498 , H01L23/31 , H01L21/56 , H01L21/48
CPC分类号： H01L23/49844 , H01L21/565 , H01L21/4857 , H01L23/3107 , H01L23/49822 , H01L23/49833
摘要： A semiconductor package includes a first power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the first power electronics carrier, and a first pair of metal pads that are immediately laterally adjacent one another and are low-voltage difference nodes of the semiconductor package, a second pair of metal pads that are immediately laterally adjacent one another and are high-voltage difference nodes of the semiconductor package, and an encapsulant body of electrically insulating material that encapsulates the power semiconductor die and the first and second pairs of metal pads, wherein the first pair of the metal pads are laterally isolated from one another by a first minimum separation distance, and wherein the second pair of the metal pads are laterally isolated from one another by a second minimum separation distance that is greater than the first minimum separation distance.
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公开(公告)号：US20210043603A1
公开(公告)日：2021-02-11
申请号：US17078460
申请日：2020-10-23
发明人： Thorsten Meyer , Gerald Ofner , Stephan Bradl , Stefan Miethaner , Alexander Heinrich , Horst Theuss , Peter Scherl
IPC分类号： H01L23/00 , H01L23/495 , H01L21/677 , H01L21/56 , H01L21/67 , H01L21/48 , H01L21/78 , H01L23/31
摘要： A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.
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公开(公告)号：US10566309B2
公开(公告)日：2020-02-18
申请号：US15284580
申请日：2016-10-04
发明人： Thorsten Meyer , Gerald Ofner , Peter Scherl , Stephan Bradl , Stefan Miethaner , Alexander Heinrich , Horst Theuss
摘要： A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.
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