公开(公告)号：US20110233777A1

公开(公告)日：2011-09-29

申请号：US13154550

申请日：2011-06-07

Applicant: Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

Inventor： Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract translation: 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US20070222054A1

公开(公告)日：2007-09-27

申请号：US11743660

申请日：2007-05-02

Applicant: David Hembree

Inventor： David Hembree

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  B23K20/004 ,  B23K20/005 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45644 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48455 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/78301 ,  H01L2224/8121 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/20751 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K3/4046 ,  H05K2201/10287 ,  H05K2203/049 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49162 ,  Y10T29/49169 ,  Y10T29/53213 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Abstract translation: 用于通过导线互连制造半导体部件的方法包括提供具有电路侧，背面和通孔的基板的步骤。 该方法还包括以下步骤：将导线穿过通孔，在背面的导线上形成接触，在电路侧的导线上形成接合接触，然后将线从接合接触件断开。 通线互连包括通孔中的导线，背侧的触点和电路侧的接合触点。 背面的触点和电路侧的接合触点允许多个部件与相邻部件之间的电连接层叠。 用于执行该方法的系统包括具有通孔的基板和具有接合毛细管的引线接合器，所述接合毛细管被配置为使线穿过通孔，并形成接触和接合接触。 半导体部件可用于形成用于电接合或测试其它半导体部件的芯片级部件，晶片级部件，堆叠部件或互连部件。

公开(公告)号：US20070167000A1

公开(公告)日：2007-07-19

申请号：US11712815

申请日：2007-03-01

Applicant: Alan Wood ,  David Hembree

Inventor： Alan Wood ,  David Hembree

IPC: H01L21/4763

CPC classification number: H01L23/02 ,  B33Y70/00 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/85001 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85121 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00015 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

Abstract translation: 半导体部件包括具有基板接触的半导体基板和与该基板接触部接合的贯通线互连（TWI）。 通线互连（TWI）包括通过基板接触和基板的通孔，连接到基板触点的通孔中的导线和线上的触点。 堆叠的半导体部件包括半导体衬底和堆叠在衬底上并结合到衬底上的通孔互连的第二半导体衬底。 一种用于制造具有通孔布线的半导体部件的方法包括以下步骤：提供具有基板接触的半导体基板，通过基板接触形成通孔，并且部分地穿过基板，将导线放置在通孔中，将导线接合到 衬底接触，然后从第二侧使衬底变薄以暴露线上的接触。 用于制造半导体部件的系统包括被配置为将导线放置在通路中并且在导线和基板接触之间形成接合连接的接合毛细管。

公开(公告)号：US20060043509A1

公开(公告)日：2006-03-02

申请号：US10925502

申请日：2004-08-24

Applicant: Charles Watkins ,  David Hembree ,  Peter Benson ,  Salman Akram

Inventor： Charles Watkins ,  David Hembree ,  Peter Benson ,  Salman Akram

IPC: H01L21/00 ,  H01L27/14 ,  H01L31/0232

CPC classification number: H01L27/14625 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/1469 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging device further includes a cover over the image sensor and a plurality of interconnects in and/or on the cover that are electrically coupled to corresponding bond-pads of the die. The interconnects provide external electrical contacts for the bond-pads of the die. The interconnects can extend through the cover or along a surface of the cover.

公开(公告)号：US20060008739A1

公开(公告)日：2006-01-12

申请号：US11216938

申请日：2005-08-31

Applicant: Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

Inventor： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

IPC: G03C1/00

CPC classification number: G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

Abstract: Materials for use in programmed material consolidation processes, such as stereolithography, include a selectively consolidatable material and a filler. The filler may be included to optimize one or more physical properties of the material. The material is both selectively consolidatable and includes the desired physical property. Examples of physical properties that may optimized in a selectively consolidatable compound by mixing a filler material with a selectively consolidatable material include, without limitation, coefficient of thermal expansion, rigidity, fracture toughness, thermal stability, and strength.

Abstract translation: 用于程序化材料固结方法（例如立体光刻）的材料包括可选择的可固结材料和填料。 可以包括填料以优化材料的一种或多种物理性质。 该材料既可选择性地整合，并且包括所需的物理性质。 通过将填充材料与可选择性地可固结的材料混合可以在可选择地可固化的化合物中优化的物理性质的实例包括但不限于热膨胀系数，刚性，断裂韧性，热稳定性和强度。

公开(公告)号：US20060003569A1

公开(公告)日：2006-01-05

申请号：US11210606

申请日：2005-08-23

Applicant: Warren Farnworth ,  Alan Wood ,  James Wark ,  David Hembree ,  Syed Ahmad ,  Michael Hess ,  John Jacobson

Inventor： Warren Farnworth ,  Alan Wood ,  James Wark ,  David Hembree ,  Syed Ahmad ,  Michael Hess ,  John Jacobson

IPC: H01L21/44

CPC classification number: H01L23/544 ,  B33Y30/00 ,  B33Y80/00 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/81 ,  H01L24/83 ,  H01L2223/5448 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11005 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/16 ,  H01L2224/293 ,  H01L2224/81011 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.

公开(公告)号：US20060003255A1

公开(公告)日：2006-01-05

申请号：US11216599

申请日：2005-08-31

Applicant: Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

Inventor： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

IPC: G03C1/492

CPC classification number: G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

Abstract: Methods for optimizing physical properties of selectively consolidatable materials, such as photoimageable materials, include mixing filler materials with the selectively consolidatable materials. The resulting compound has the desired physical property, as well as selective consolidatability. Examples of physical properties that may optimized in a selectively consolidatable compound by mixing a filler material with a selectively consolidatable material include, without limitation, coefficient of thermal expansion, rigidity, fracture toughness, thermal stability, and strength.

Abstract translation: 用于优化选择性可固结材料（例如可光成像材料）的物理性质的方法包括将填料与可选择的可固结材料混合。 所得化合物具有所需的物理性质以及选择性的可固化性。 通过将填充材料与可选择性地可固结的材料混合可以在可选择地可固化的化合物中优化的物理性质的实例包括但不限于热膨胀系数，刚性，断裂韧性，热稳定性和强度。

公开(公告)号：US20060001139A1

公开(公告)日：2006-01-05

申请号：US11216617

申请日：2005-08-31

Applicant: Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

Inventor： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

IPC: H01L23/02

CPC classification number: G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

Abstract: A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.

Abstract translation: 在半导体衬底的薄化或后研磨以及后稀化处理期间与半导体衬底一起使用的支撑结构包括基本上沿半导体衬底的外周延伸并且围绕半导体衬底的外周延伸的部分，以使薄化半导体 基板具有刚性。 支撑结构可以被配置为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。

公开(公告)号：US20050233482A1

公开(公告)日：2005-10-20

申请号：US11152433

申请日：2005-06-14

Applicant: Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

Inventor： Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

IPC: G01R1/073 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01R13/24 ,  H05K3/32 ,  H05K3/40 ,  H05K7/06 ,  H05K7/10

CPC classification number: G01R1/0735 ,  G01R1/07314 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01R12/714 ,  H01R13/24 ,  H01R2201/20 ,  H05K3/326 ,  H05K7/1069 ,  H05K2201/0314 ,  H05K2201/09036 ,  H05K2201/10378 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599

Abstract: A compliant contact pin contactor card method for making is provided. A compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.

Abstract translation: 提供一种兼容的接触针接触器卡制造方法。 柔性接触销组件包括由衬底的一部分形成的接触针，其中触发销通过柔性耦合结构顺应地保持悬挂在衬底内。 衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。 接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。 在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

公开(公告)号：US20050211236A1

公开(公告)日：2005-09-29

申请号：US11137048

申请日：2005-05-25

Applicant: Salman Akram ,  Derek Gochnour ,  Michael Hess ,  David Hembree

Inventor： Salman Akram ,  Derek Gochnour ,  Michael Hess ,  David Hembree

IPC: B23P17/00 ,  B26D3/00 ,  B28D1/32 ,  B28D5/02 ,  H01L21/00 ,  H01L21/301 ,  H01L23/58 ,  H01L29/00 ,  H05K3/02 ,  H05K3/20 ,  H05K3/30

CPC classification number: H01L21/67092 ,  B28D5/024 ,  B28D5/029 ,  Y10T83/0222 ,  Y10T83/0363 ,  Y10T83/04 ,  Y10T83/0524 ,  Y10T83/7726 ,  Y10T83/7809 ,  Y10T83/7868

Abstract: A saw for dicing substrates, such as semiconductor wafers, that has one or more variable indexing capabilities and two or more blades. One of the blades may be moved laterally or vertically, independent of one or more other blades.

Abstract translation: 用于具有一个或多个可变分度能力的切割基板（例如半导体晶片）的锯和两个或更多个叶片。 一个叶片可以横向或垂直地移动，而与一个或多个其它叶片无关。