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184 条记录 (耗时 0.022 秒)

    Power managers for an integrated circuit
    2.
    发明授权
    Power managers for an integrated circuit 有权

    公开(公告)号：US11362645B2

    公开(公告)日：2022-06-14

    申请号：US16928311

    申请日：2020-07-14

    申请人： Mosaid Technologies Incorporated

    发明人： Barry Alan Hoberman ,  Daniel L. Hillman ,  Jon Shiell

    IPC分类号： H03K3/012 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H02J4/00

    摘要： Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each power island of the plurality of power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.

    NON-VOLATILE MEMORY DEVICE WITH CONCURRENT BANK OPERATIONS
    3.
    发明申请
    NON-VOLATILE MEMORY DEVICE WITH CONCURRENT BANK OPERATIONS 有权

    公开(公告)号：US20210327503A1

    公开(公告)日：2021-10-21

    申请号：US17246190

    申请日：2021-04-30

    申请人： Mosaid Technologies Incorporated

    发明人： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

    IPC分类号： G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    Process, voltage, temperature independent switched delay compensation scheme
    5.
    发明授权
    Process, voltage, temperature independent switched delay compensation scheme 有权
    过程，电压，温度独立的开关延迟补偿方案

    公开(公告)号：US08897411B2

    公开(公告)日：2014-11-25

    申请号：US13741994

    申请日：2013-01-15

    申请人： Mosaid Technologies Incorporated

    发明人： Gurpreet Bhullar ,  Graham Allan

    IPC分类号： H03D3/24

    CPC分类号： H03L7/06 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/089 ,  H03L7/093

    摘要： A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

    摘要翻译： 一种用于延迟锁定环路的延迟补偿电路，其包括具有精细延迟线的主延迟线，该延迟线包括精细延迟元件和包括粗延迟元件的粗延迟线，该主延迟线由控制器控制，该延迟补偿电路包括： 用于对粗略延迟元件进行建模的可调精细延迟，用于将可调节精细延迟控制为与粗略延迟元件基本相同的值的计数器，用于将系统时钟的表示应用于延迟补偿电路的电路 以及从计数器向控制器施加精细延迟计数的电路，用于将主延迟线的精细延迟线调整为与主延迟线的粗略延迟元件基本相同的值。

    Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance
    8.
    发明授权
    Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance 有权
    具有多极性位的相变存储器具有增强的耐久性和容错性

    公开(公告)号：US08780622B2

    公开(公告)日：2014-07-15

    申请号：US13860724

    申请日：2013-04-11

    申请人： Mosaid Technologies Incorporated

    发明人： Jin-Ki Kim ,  Peter B. Gillingham ,  William F. Petrie

    IPC分类号： G11C11/00 ,  G11C7/10

    CPC分类号： G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C2029/0411 ,  G11C2211/5647

    摘要： A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data value or the inversion of the data value. In one embodiment an odd number of set polarity bits indicates that the data bits represent the inversion of the data value and an even number of set polarity bits indicates that the data bits represent the data value. The PCM apparatus has enhanced endurance and improved error tolerance.

    摘要翻译： 一种相变存储器（PCM）装置，包括用于存储表示数据值的数据位或数据值反转的数据位的数据场，以及用于存储用于指示存储在数据中的数据位的多个极性位的极性场 字段表示数据值或数据值的反转。 在一个实施例中，奇数个设置极性位指示数据位表示数据值的反转，偶数个设置的极性位表示数据位表示数据值。 PCM装置具有增强的耐久性和改进的误差容限。

    SCALABLE MEMORY SYSTEM
    9.
    发明申请
    SCALABLE MEMORY SYSTEM 审中-公开
    可扩展存储系统

    公开(公告)号：US20140195715A1

    公开(公告)日：2014-07-10

    申请号：US14172946

    申请日：2014-02-05

    申请人： MOSAID TECHNOLOGIES INCORPORATED

    发明人： Jin-Ki KIM ,  HakJune OH ,  Hong Beom PYEON ,  Steven PRZYBYLSKI

    IPC分类号： G11C7/10 ,  G06F12/06

    CPC分类号： G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

    摘要翻译： 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

    NONVOLATILE MEMORY WITH SPLIT SUBSTRATE SELECT GATES AND HEIRARCHICAL BITLINE CONFIGURATION
    10.
    发明申请
    NONVOLATILE MEMORY WITH SPLIT SUBSTRATE SELECT GATES AND HEIRARCHICAL BITLINE CONFIGURATION 有权
    具有分离基板的非易失性存储器选择栅极和引线配置

    公开(公告)号：US20140192596A1

    公开(公告)日：2014-07-10

    申请号：US13830054

    申请日：2013-03-14

    申请人： MOSAID TECHNOLOGIES INCORPORATED

    发明人： Hyoung Seub RHIE

    IPC分类号： G11C16/02

    CPC分类号： G11C11/5635 ,  G11C16/0483 ,  G11C16/14

    摘要： Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.

    摘要翻译： 通常，本公开提供了一种具有分级位线结构的非易失性存储器件，用于防止施加到存储器阵列的一组存储器单元的擦除电压泄漏到不需要擦除的其他组。 本地位线耦合到每组存储器单元的存储单元。 每个本地位线可以在所选择的组的读取操作期间选择性地连接到全局位线，并且当选择特定组以进行擦除时，在擦除操作期间，可以将全局位线与全局位线断开。 选择用于将特定组存储器单元的每个位线电连接到全局位线的器件具有与这些存储器单元的主体电隔离的器件体。