公开(公告)号：US20130070539A1

公开(公告)日：2013-03-21

申请号：US13650580

申请日：2012-10-12

申请人： MOSAID TECHNOLOGIES INCORPORATED

发明人： Jin-Ki KIM ,  HakJune OH

IPC分类号： G11C11/402 ,  G11C7/10

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

公开(公告)号：US20230253036A1

公开(公告)日：2023-08-10

申请号：US18109390

申请日：2023-02-14

申请人： Mosaid Technologies Incorporated

发明人： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC分类号： G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/06

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US20210327503A1

公开(公告)日：2021-10-21

申请号：US17246190

申请日：2021-04-30

申请人： Mosaid Technologies Incorporated

发明人： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC分类号： G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US20140195715A1

公开(公告)日：2014-07-10

申请号：US14172946

申请日：2014-02-05

申请人： MOSAID TECHNOLOGIES INCORPORATED

发明人： Jin-Ki KIM ,  HakJune OH ,  Hong Beom PYEON ,  Steven PRZYBYLSKI

IPC分类号： G11C7/10 ,  G06F12/06

CPC分类号： G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

摘要翻译： 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

公开(公告)号：US20140173322A1

公开(公告)日：2014-06-19

申请号：US14185401

申请日：2014-02-20

申请人： MOSAID TECHNOLOGIES INCORPORATED

发明人： Hong Beom PYEON ,  HakJune OH

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  G06F1/04 ,  G11C5/00 ,  G11C5/066 ,  G11C7/20

摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

摘要翻译： 各种存储器件（例如，DRAM，闪存）串联连接。 存储器件需要它们的标识符（ID）。 每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。 命令数据和先前生成的ID数据被同步地注册。 注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。 计算是一个加法或减法。 通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。 响应于解释的ID和时钟来控制时钟延迟。 根据受控时钟延迟，以分组为基础提供新的ID。 在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

公开(公告)号：US20140133242A1

公开(公告)日：2014-05-15

申请号：US14156047

申请日：2014-01-15

申请人： MOSAID Technologies Incorporated

发明人： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC分类号： G11C16/26

CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US20130067118A1

公开(公告)日：2013-03-14

申请号：US13671248

申请日：2012-11-07

申请人： Mosaid Technologies Incorporated

发明人： Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM ,  Shuji SUMI

IPC分类号： G06F13/14

CPC分类号： G06F13/4243

摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

摘要翻译： 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。 在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。 根据设备类型匹配确定，DT与所生成或接收的ID组合。 组合的DT和ID作为传送到下一个设备的分组。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 参考提供给互连设备的设备类型，依次生成ID。 将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

公开(公告)号：US20130119542A1

公开(公告)日：2013-05-16

申请号：US13675163

申请日：2012-11-13

申请人： MOSAID Technologies Incorporated

发明人： HakJune OH

IPC分类号： H01L23/498

CPC分类号： H01L25/0657 ,  H01L23/49816 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2224/32145 ,  H01L2924/00 ,  H01L2924/00014

摘要： A multi-chip package has a substrate, and a plurality of memory dies stacked on the substrate. A plurality of buffer dies each has an input and an output. The input of a first buffer die is connectable to an external input. The output of a last buffer die of the plurality of buffer dies is connectable to an external output. Each of the remaining inputs and outputs is connected respectively to an output or an input of another of the plurality of buffer dies to form a serial connection between the plurality of buffer dies. Each of the memory dies is connected to one of the buffer dies, such that each buffer die is connected to its respective memory dies in parallel arrangement. A memory device having multiple serially interconnected MCPs and a controller is also described.

摘要翻译： 多芯片封装具有基板和堆叠在基板上的多个存储器管芯。 多个缓冲模具各自具有输入和输出。 第一缓冲管芯的输入可连接到外部输入端。 多个缓冲管芯的最后一个缓冲管芯的输出可连接到外部输出。 每个剩余的输入和输出分别连接到多个缓冲管芯中另一个的输出端或输入端，以形成多个缓冲管芯之间的串联连接。 每个存储器管芯连接到缓冲管芯之一，使得每个缓冲管芯以并联布置连接到其各自的存储器管芯。 还描述了具有多个串行互连的MCP和控制器的存储器件。

公开(公告)号：US20130229874A1

公开(公告)日：2013-09-05

申请号：US13867437

申请日：2013-04-22

申请人： MOSAID TECHNOLOGIES INCORPORATED

发明人： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US20130073754A1

公开(公告)日：2013-03-21

申请号：US13676606

申请日：2012-11-14

申请人： Mosaid Technologies Incorporated

发明人： Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM

IPC分类号： G06F13/00

CPC分类号： G06F13/4291

摘要： A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration.

摘要翻译： 一种方法或设备操作串行互连配置中的多个设备以建立每个设备的设备标识符（ID）。 输入信号通过使用也由第一设备用于输入其它信息（例如，数据，命令，控制信号）的输入通过串行互连传输到第一设备。 发生电路响应于输入信号产生装置ID。 传输电路然后通过第一设备的串行输出将与设备ID相关联的输出信号传送到第二设备。 串行输出也由第一设备用于在串行互连配置中向另一设备输出其他信息（例如，信号，数据）。