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    VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY
    1.
    发明申请
    VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY 审中-公开
    低压转换器用于高速存储器

    公开(公告)号：US20140071781A1

    公开(公告)日：2014-03-13

    申请号：US14080302

    申请日：2013-11-14

    申请人： MOSAID Technologies Incorporated

    发明人： Hong Beom PYEON ,  Bruce MILLAR

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

    摘要： A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

    摘要翻译： 适用于高速存储器件的降压转换器（VDC）。 VDC包括一个稳定的驱动器和有源驱动器以及至少一个额外的晶体管。 稳定的驱动器和有源驱动器在器件启动期间由晶体管开关耦合，以提供对工作电压和电流的快速上升。 启动后，稳定的驱动器和主动驱动功能保持稳定的工作电压和电流。 在发出表示存储器的读取，写入和/或刷新的活动命令时，附加晶体管被数字控制以驱动工作电压和电流。 以这种方式，附加晶体管对存储器阵列中的活动引起的工作电压和电流的波动提供快速补偿。

    METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE
    2.
    发明申请
    METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE 有权
    配置混合磁盘驱动器的非易失性存储器的方法

    公开(公告)号：US20130046921A1

    公开(公告)日：2013-02-21

    申请号：US13655582

    申请日：2012-10-19

    申请人： MOSAID Technologies Incorporated

    发明人： Hong Beom PYEON

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0664 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/068 ,  G06F9/4408 ,  G06F12/0868 ,  G06F2212/217 ,  Y02D10/13 ,  Y02D10/154

    摘要： A system, method and machine-readable medium are provided to configure a non-volatile memory (NVM) including a plurality of NVM modules, in a system having a hard disk drive (HDD) and an operating system (O/S). In response to a user selection of a hybrid drive mode for the NVM, the plurality of NVM modules are ranked according to speed performance. Boot portions of the O/S are copied to a highly ranked NVM module, or a plurality of highly ranked NVM modules, and the HDD and the highly ranked NVM modules are assigned as a logical hybrid drive of the computer system. Ranking each of the plurality of NVM modules can include carrying out a speed performance test. This approach can provide hybrid disk performance using conventional hardware, or enhance performance of an existing hybrid drive, while taking into account relative performance of available NVM modules.

    摘要翻译： 在具有硬盘驱动器（HDD）和操作系统（O / S）的系统中，提供了一种系统，方法和机器可读介质来配置包括多个NVM模块的非易失性存储器（NVM）。 响应于用户选择NVM的混合驱动模式，根据速度性能对多个NVM模块进行排序。 O / S的引导部分被复制到高排名的NVM模块或多个高排名的NVM模块，并且HDD和高排名的NVM模块被分配为计算机系统的逻辑混合驱动器。 对多个NVM模块中的每一个进行排序可以包括进行速度性能测试。 这种方法可以使用常规硬件提供混合磁盘性能，或提高现有混合驱动器的性能，同时考虑可用的NVM模块的相对性能。

    NON-VOLATILE MEMORY DEVICE WITH CONCURRENT BANK OPERATIONS
    7.
    发明申请
    NON-VOLATILE MEMORY DEVICE WITH CONCURRENT BANK OPERATIONS 有权

    公开(公告)号：US20210327503A1

    公开(公告)日：2021-10-21

    申请号：US17246190

    申请日：2021-04-30

    申请人： Mosaid Technologies Incorporated

    发明人： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

    IPC分类号： G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    SCALABLE MEMORY SYSTEM
    8.
    发明申请
    SCALABLE MEMORY SYSTEM 审中-公开
    可扩展存储系统

    公开(公告)号：US20140195715A1

    公开(公告)日：2014-07-10

    申请号：US14172946

    申请日：2014-02-05

    申请人： MOSAID TECHNOLOGIES INCORPORATED

    发明人： Jin-Ki KIM ,  HakJune OH ,  Hong Beom PYEON ,  Steven PRZYBYLSKI

    IPC分类号： G11C7/10 ,  G06F12/06

    CPC分类号： G11C7/1042 ,  G06F12/0623 ,  G06F13/1694 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/10 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

    摘要翻译： 存储器系统架构具有串行连接的存储器件。 内存系统具有可扩展性，可以包含任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间进行通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

    PACKET DATA ID GENERATION FOR SERIALLY INTERCONNECTED DEVICES
    9.
    发明申请
    PACKET DATA ID GENERATION FOR SERIALLY INTERCONNECTED DEVICES 审中-公开
    用于串行互连设备的分组数据ID生成

    公开(公告)号：US20140173322A1

    公开(公告)日：2014-06-19

    申请号：US14185401

    申请日：2014-02-20

    申请人： MOSAID TECHNOLOGIES INCORPORATED

    发明人： Hong Beom PYEON ,  HakJune OH

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12 ,  G06F1/04 ,  G11C5/00 ,  G11C5/066 ,  G11C7/20

    摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

    摘要翻译： 各种存储器件（例如，DRAM，闪存）串联连接。 存储器件需要它们的标识符（ID）。 每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。 命令数据和先前生成的ID数据被同步地注册。 注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。 计算是一个加法或减法。 通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。 响应于解释的ID和时钟来控制时钟延迟。 根据受控时钟延迟，以分组为基础提供新的ID。 在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

    MEMORY WITH OUTPUT CONTROL
    10.
    发明申请
    MEMORY WITH OUTPUT CONTROL 有权
    带输出控制的存储器

    公开(公告)号：US20140133242A1

    公开(公告)日：2014-05-15

    申请号：US14156047

    申请日：2014-01-15

    申请人： MOSAID Technologies Incorporated

    发明人： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

    IPC分类号： G11C16/26

    CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。