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    Non-volatile memory device with concurrent bank operations
    1.
    发明授权
    Non-volatile memory device with concurrent bank operations 有权

    公开(公告)号：US11600323B2

    公开(公告)日：2023-03-07

    申请号：US17246190

    申请日：2021-04-30

    申请人： Mosaid Technologies Incorporated

    发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    IPC分类号： G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/06

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    NAND flash memory having multiple cell substrates
    2.
    发明授权
    NAND flash memory having multiple cell substrates 有权
    NAND闪存具有多个单元基板

    公开(公告)号：US09070461B2

    公开(公告)日：2015-06-30

    申请号：US14032816

    申请日：2013-09-20

    申请人： MOSAID Technologies Incorporated

    发明人： Jin-Ki Kim

    IPC分类号： G11C11/34 ,  G11C16/16 ,  H01L27/115

    CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

    摘要： A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

    摘要翻译： 具有连接到页缓冲器的存储器阵列的多个位线的NAND闪存库，其中连接到相同位线的NAND单元串形成在至少两个阱扇区中。 在擦除操作期间，至少一个阱区可以选择性地耦合到擦除电压，使得未选择的阱区被禁止接收擦除电压。 当井区的面积减小时，每个井区的电容相应减小。 因此，当电荷泵电路驱动能力保持不变时，可以获得NAND闪速存储单元相对于单个存储器组的更高速擦除。 或者，通过将具有特定面积的阱段与具有降低的驱动能力的电荷泵相匹配来获得对应于单阱存储器组的恒定擦除速度。 降低的驱动电容电荷泵将占用较少的半导体芯片面积，从而降低成本。

    Dynamic random access memory with fully independent partial array refresh function
    3.
    发明授权
    Dynamic random access memory with fully independent partial array refresh function 有权
    具有完全独立的部分阵列刷新功能的动态随机存取存储器

    公开(公告)号：US08743643B2

    公开(公告)日：2014-06-03

    申请号：US13650580

    申请日：2012-10-12

    申请人： Mosaid Technologies Incorporated

    发明人： Jin-Ki Kim ,  HakJune Oh

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

    摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

    摘要翻译： 动态随机存取存储器件包括多个存储器子块。 每个子块具有连接多个数据存储单元的多个字线。 部分阵列自刷新（PASR）配置设置是独立制作的。 根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。 可以选择子块地址的任何种类的组合。 因此，存储器子块被完全独立地刷新。 用于数据保留的用户可选择的存储器阵列提供有效的存储器控​​制编程，特别是对于低功率移动应用。

    Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
    4.
    发明授权
    Apparatus and method for producing device identifiers for serially interconnected devices of mixed type 有权
    用于生产混合型串联互连设备的设备标识符的设备和方法

    公开(公告)号：US08694692B2

    公开(公告)日：2014-04-08

    申请号：US13671248

    申请日：2012-11-07

    申请人： Mosaid Technologies Incorporated

    发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

    IPC分类号： G06F3/00

    CPC分类号： G06F13/4243

    摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

    摘要翻译： 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。 在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。 根据设备类型匹配确定，DT与所生成或接收的ID组合。 组合的DT和ID作为传送到下一个设备的分组。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 参考提供给互连设备的设备类型，依次生成ID。 将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

    Non-volatile memory device having configurable page size
    5.
    发明授权
    Non-volatile memory device having configurable page size 有权
    具有可配置页面大小的非易失性存储器件

    公开(公告)号：US08675408B2

    公开(公告)日：2014-03-18

    申请号：US13743899

    申请日：2013-01-17

    申请人： MOSAID Technologies Incorporated

    发明人： Jin-Ki Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

    摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

    摘要翻译： 具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。 每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。 在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。 通过选择性地调整存储体的页面大小，相应地调整块大小。

    Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance
    7.
    发明授权
    Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance 有权
    具有多极性位的相变存储器具有增强的耐久性和容错性

    公开(公告)号：US08780622B2

    公开(公告)日：2014-07-15

    申请号：US13860724

    申请日：2013-04-11

    申请人： Mosaid Technologies Incorporated

    发明人： Jin-Ki Kim ,  Peter B. Gillingham ,  William F. Petrie

    IPC分类号： G11C11/00 ,  G11C7/10

    CPC分类号： G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C2029/0411 ,  G11C2211/5647

    摘要： A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data value or the inversion of the data value. In one embodiment an odd number of set polarity bits indicates that the data bits represent the inversion of the data value and an even number of set polarity bits indicates that the data bits represent the data value. The PCM apparatus has enhanced endurance and improved error tolerance.

    摘要翻译： 一种相变存储器（PCM）装置，包括用于存储表示数据值的数据位或数据值反转的数据位的数据场，以及用于存储用于指示存储在数据中的数据位的多个极性位的极性场 字段表示数据值或数据值的反转。 在一个实施例中，奇数个设置极性位指示数据位表示数据值的反转，偶数个设置的极性位表示数据位表示数据值。 PCM装置具有增强的耐久性和改进的误差容限。

    Memory with output control
    9.
    发明授权
    Memory with output control 有权
    内存带输出控制

    公开(公告)号：US08654601B2

    公开(公告)日：2014-02-18

    申请号：US13867437

    申请日：2013-04-22

    申请人： Mosaid Technologies Incorporated

    发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

    Non-Volatile Semiconductor Memory with Page Erase
    10.
    发明申请
    Non-Volatile Semiconductor Memory with Page Erase 审中-公开
    非易失性半导体存储器，具有页擦除

    公开(公告)号：US20130336063A1

    公开(公告)日：2013-12-19

    申请号：US13969184

    申请日：2013-08-16

    申请人： MOSAID Technologies Incorporated

    发明人： Jin-Ki Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/04 ,  G11C7/20 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  G11C16/3445

    摘要： In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

    摘要翻译： 在非易失性存储器中，少于一个完整的块可能会被擦除为一个或多个页面。 通过通过晶体管将选择电压施加到多个选定字线中的每一个，并且通过传输晶体管将未选择的电压施加到所选块的多个未选择字线中的每一个。 将衬底电压施加到所选块的衬底。 可以将公共选择电压施加到每个所选择的字线，并且可以将公共未选择电压施加到每个未选择的字线。 选择和取消选择电压可以应用于选择块的任何字线。 页面擦除验证操作可以应用于具有多个擦除页面和多个非寻址页面的块。