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    Vertical cross-point arrays for ultra-high-density memory applications
    2.
    发明授权
    Vertical cross-point arrays for ultra-high-density memory applications 有权

    公开(公告)号：US10790334B2

    公开(公告)日：2020-09-29

    申请号：US15633050

    申请日：2017-06-26

    申请人： Unity Semiconductor Corporation

    发明人： Bruce Lynn Bateman

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements
    3.
    发明授权
    Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements 有权

    公开(公告)号：US10788993B2

    公开(公告)日：2020-09-29

    申请号：US16811401

    申请日：2020-03-06

    申请人： Unity Semiconductor Corporation

    发明人： Chang Hua Siau

    IPC分类号： G11C11/00 ,  G06F3/06 ,  G11C11/419 ,  G11C13/00 ,  G11C5/06 ,  G11C8/08

    摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

    Vertical gate NAND memory devices
    10.
    发明授权
    Vertical gate NAND memory devices 有权
    垂直门NAND存储器件

    公开(公告)号：US09570459B2

    公开(公告)日：2017-02-14

    申请号：US14314622

    申请日：2014-06-25

    申请人： Unity Semiconductor Corporation

    发明人： Bruce Lynn Bateman

    IPC分类号： H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04 ,  G11C16/34

    CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926

    摘要： In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line.

    摘要翻译： 在一个示例中，设备包括垂直堆叠的存储器单元。 垂直堆栈的每个存储单元可以包括多于一个存储元件。 第一垂直栅极线可以耦合到每个存储器单元中的存储器元件中的第一个，并且第二垂直栅极线可以耦合到每个存储器单元中的第二个存储器元件。 第一垂直栅极线可以与第二垂直栅极线电隔离。