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    Cross point memory array exhibiting a characteristic hysteresis
    81.
    发明申请
    Cross point memory array exhibiting a characteristic hysteresis 有权
    具有特征滞后的交叉点存储器阵列

    公开(公告)号：US20050128840A1

    公开(公告)日：2005-06-16

    申请号：US11047952

    申请日：2005-01-31

    Applicant: Darrell Rinerson

    Inventor： Darrell Rinerson

    IPC: G11C11/56 ,  G11C13/00 ,  G11C7/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  G11C2213/77

    Abstract: Providing a cross point memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.

    Abstract translation: 提供具有表现出特征滞后的存储插件的交叉点存储器阵列。 存储插头表现出滞后现象，在低电阻状态下，第一写入阈值电压是高于其上施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，低于该电压脉冲将改变电阻 内存插头。 类似地，在高电阻状态下，第二写入阈值电压是低于施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，并且高于该电压脉冲将改变存储器插头的电阻。 施加到存储器插头的读取电压通常高于第一写入阈值电压并低于第二写入阈值电压。

    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
    83.
    发明授权
    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
    本地位线及其选择方法可以访问交叉点阵列中的存储器元件

    公开(公告)号：US08897050B2

    公开(公告)日：2014-11-25

    申请号：US13588461

    申请日：2012-08-17

    Applicant: Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Namala

    Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Namala

    IPC: G11C5/02 ,  H01L21/82 ,  G11C8/00 ,  G11C11/00

    CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

    Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

    Abstract translation: 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

    Device fabrication
    87.
    发明授权
    Device fabrication 有权
    器件制造

    公开(公告)号：US08569160B2

    公开(公告)日：2013-10-29

    申请号：US13665603

    申请日：2012-10-31

    Applicant: Darrell Rinerson ,  Robin Cheung

    Inventor： Darrell Rinerson ,  Robin Cheung

    IPC: H01L21/768

    CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

    Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

    DEVICE FABRICATION
    88.
    发明申请
    DEVICE FABRICATION 有权
    设备制造

    公开(公告)号：US20130059436A1

    公开(公告)日：2013-03-07

    申请号：US13665603

    申请日：2012-10-31

    Applicant: Darrell Rinerson ,  Robin Cheung

    Inventor： Darrell Rinerson ,  Robin Cheung

    IPC: H01L21/768

    CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

    Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

    Threshold Device For A Memory Array
    89.
    发明申请
    Threshold Device For A Memory Array 有权
    内存阵列的阈值设备

    公开(公告)号：US20110291067A1

    公开(公告)日：2011-12-01

    申请号：US13206460

    申请日：2011-08-09

    Applicant: JULIE CASPERSON BREWER ,  DARRELL RINERSON ,  CHRISTOPHE J. CHEVALLIER ,  WAYNE KINNEY ,  ROY LAMBERTSON ,  LAWRENCE SCHLOSS

    Inventor： JULIE CASPERSON BREWER ,  DARRELL RINERSON ,  CHRISTOPHE J. CHEVALLIER ,  WAYNE KINNEY ,  ROY LAMBERTSON ,  LAWRENCE SCHLOSS

    IPC: H01L45/00

    CPC classification number: G11C7/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

    Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

    Abstract translation: 公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。 具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。 阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。 阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。 阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

    Memory cell formation using ion implant isolated conductive metal oxide
    90.
    发明授权
    Memory cell formation using ion implant isolated conductive metal oxide 失效
    使用离子注入隔离导电金属氧化物的存储单元形成

    公开(公告)号：US08003511B2

    公开(公告)日：2011-08-23

    申请号：US12653851

    申请日：2009-12-18

    Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

    Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

    IPC: H01L21/44

    CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

    Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

    Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

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