公开(公告)号：US09257375B2

公开(公告)日：2016-02-09

申请号：US13236931

申请日：2011-09-20

申请人： Anup Bhalla ,  Yi Su ,  David Grey

发明人： Anup Bhalla ,  Yi Su ,  David Grey

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/074 ,  H01L23/3171 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/50 ,  H01L29/7827 ,  H01L2224/02166 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/30101 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.

摘要翻译： 多管芯封装具有多个引线，第一和第二半导体管芯叠加并结合在一起，形成管芯堆叠。 管芯堆叠具有相对的第一和第二面，其中第一和第二半导体管芯中的每一个具有栅极，漏极和源极区以及栅极，漏极和源极接触。 第一相对侧具有与第一组多个引线电连通的第二半导体管芯的漏极接触。 第一半导体管芯的栅极，漏极和源极接触以及第二半导体管芯的栅极和源极触点设置在所述相对侧的第二侧上并且与第二组多个引线电连通。 用于第一半导体管芯的源极的引线可以与第二半导体管芯的漏极引线相同。

公开(公告)号：US20160036331A1

公开(公告)日：2016-02-04

申请号：US14884566

申请日：2015-10-15

申请人： Kabushiki Kaisha Toshiba

发明人： Hiroshi Saito ,  Ryo Wada ,  Yuichi Goto

IPC分类号： H02M3/158 ,  H01L23/495 ,  H02M3/156 ,  H01L23/00

CPC分类号： H02M3/158 ,  G05F1/46 ,  H01L23/495 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1304 ,  H01L2924/1425 ,  H01L2924/1426 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/156 ,  H02M7/003 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In general, according to one embodiment, a semiconductor device includes a device main body, a semiconductor substrate. The device main body includes a semiconductor substrate mounting part and a first conductor provided around the semiconductor substrate mounting part. The semiconductor substrate includes a DC-to-DC converter control circuit having a detector to detect at least one of a current flowing through the first conductor and a voltage supplied to the first conductor. The semiconductor substrate is disposed on the semiconductor substrate mounting part so that the detector comes close to the first conductor.

公开(公告)号：US09245940B2

公开(公告)日：2016-01-26

申请号：US14179202

申请日：2014-02-12

申请人： QUALCOMM Incorporated

发明人： Young Kyu Song ,  Yunseo Park ,  Xiaonan Zhang ,  Ryan David Lane ,  Aristotele Hadjichristos

IPC分类号： H01L27/08 ,  H01L49/02 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L28/10 ,  H01L23/3192 ,  H01L23/5227 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/16225 ,  H01L2924/01029 ,  H01L2924/30107

摘要： An inductor design on a wafer level package (WLP) does not need to depopulate the solder balls on the die because the solder balls form part of the inductor. One terminal on the inductor couples to the die, the other terminal couples to a single solder ball on the die, and the remaining solder balls that mechanically contact the inductor remain electrically floating. The resulting device has better inductance, direct current (DC) resistance, board-level reliability (BLR), and quality factor (Q).

摘要翻译： 晶圆级封装（WLP）上的电感器设计不需要将焊球沉淀在芯片上，因为焊球形成电感器的一部分。 电感器上的一个端子耦合到管芯，另一个端子耦合到管芯上的单个焊球，并且与电感器机械接触的剩余焊球保持电浮动。 所产生的器件具有更好的电感，直流（DC）电阻，电路板级可靠性（BLR）和品质因数（Q）。

公开(公告)号：US09226400B2

公开(公告)日：2015-12-29

申请号：US13734266

申请日：2013-01-04

申请人： Murata Manufacturing Co., Ltd.

发明人： Masato Nomiya ,  Norio Sakai ,  Mitsuyoshi Nishide

IPC分类号： H05K1/03 ,  H05K1/00 ,  H05K1/16 ,  H01R4/58 ,  H05K7/10 ,  H05K1/18 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498 ,  H01L23/00 ,  H05K3/30 ,  H05K3/46

CPC分类号： H05K1/181 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K3/305 ,  H05K3/4626 ,  H05K3/4629 ,  H05K2201/0116 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1147 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

摘要： In a method for manufacturing a multilayer ceramic electronic device, a multilayer ceramic element assembly including laminated unsintered ceramic base material layers, a first conductor pattern, a seat portion disposed in a surface of the multilayer ceramic element assembly and arranged to mount a surface mount electronic device thereon, a second conductor pattern connected to the surface mount electronic device, and a resin introduction portion located outside a vertically projected region of the surface mount electronic device and arranged to introduce a resin to the seat portion is prepared. The multilayer ceramic element assembly is fired and the surface mount electronic device is mounted on the seat portion of the fired multilayer ceramic element assembly with the second conductor pattern therebetween. The resin is filled from the resin introduction portion into the seat portion and between the seat portion and the surface mount electronic device and is cured.

摘要翻译： 在多层陶瓷电子器件的制造方法中，包括层叠的未烧结的陶瓷基材层的多层陶瓷元件组件，第一导体图案，配置在所述多层陶瓷元件组件的表面的座部， 设置在其上，连接到表面安装电子设备的第二导体图案，以及位于表面安装电子设备的垂直投影区域外部并且布置成将树脂引入座部的树脂引入部分。 烧结多层陶瓷元件组件，并且表面安装电子器件安装在烧制的多层陶瓷元件组件的座部上，其间具有第二导体图案。 树脂从树脂引入部分填充到座椅部分中，并且在座椅部分和表面安装电子装置之间填充并固化。

公开(公告)号：US09219108B2

公开(公告)日：2015-12-22

申请号：US14625390

申请日：2015-02-18

申请人： Renesas Electronics Corporation

发明人： Takuo Funaya ,  Hiromi Shigihara ,  Hisao Shigihara

IPC分类号： H01L49/02 ,  H01L23/495 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00

CPC分类号： H01L28/10 ,  H01L23/49575 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0617 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06102 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device including a semiconductor substrate having a main surface; a first insulating layer formed on the main surface and having a first main surface, the first main surface including a first region and a second region without the first area; a first coil formed on the first region of the first insulating layer; a plurality of first wirings formed on the second region of the first insulating layer; a second insulating layer formed on the first coil and on the first wirings, the second insulating layer having a second main surface; a third insulating layer formed on the second main surface above the first region of the first insulating layer and having a third main surface; and a second coil formed on the third main surface of the third insulating layer.

摘要翻译： 一种半导体器件，包括具有主表面的半导体衬底; 形成在所述主表面上并具有第一主表面的第一绝缘层，所述第一主表面包括第一区域和没有所述第一区域的第二区域; 形成在所述第一绝缘层的所述第一区域上的第一线圈; 形成在所述第一绝缘层的所述第二区域上的多个第一布线; 形成在所述第一线圈和所述第一布线上的第二绝缘层，所述第二绝缘层具有第二主表面; 第三绝缘层，形成在所述第一绝缘层的所述第一区域上方的所述第二主表面上，并具有第三主表面; 以及形成在第三绝缘层的第三主表面上的第二线圈。

公开(公告)号：US20150364393A1

公开(公告)日：2015-12-17

申请号：US14829026

申请日：2015-08-18

申请人： ROHM CO., LTD.

发明人： Hirotaka OTAKE ,  Toshio HANADA

IPC分类号： H01L23/053 ,  H01L23/16 ,  H01L25/065 ,  H01L25/16 ,  H01L23/367 ,  H01L23/492

CPC分类号： H01L23/053 ,  H01L21/566 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/48 ,  H01L23/4924 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/165 ,  H01L25/18 ,  H01L29/0603 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/05553 ,  H01L2224/40137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： There is provided a power module semiconductor device allowing reduction in size and weight of a thin type SiC power module. The power module semiconductor device includes: a ceramic substrate; a first pattern of a first copper plate layer disposed on a surface of the ceramic substrate; a first semiconductor chip disposed on the first pattern; a first pillar connection electrode disposed on the first pattern; and an output terminal connected to the first pillar connection electrode.

摘要翻译： 提供了能够减小薄型SiC功率模块的尺寸和重量的功率模块半导体器件。 功率模块半导体器件包括：陶瓷衬底; 设置在陶瓷基板的表面上的第一铜板层的第一图案; 设置在第一图案上的第一半导体芯片; 设置在第一图案上的第一柱连接电极; 以及连接到第一支柱连接电极的输出端子。

公开(公告)号：US09209173B2

公开(公告)日：2015-12-08

申请号：US13415384

申请日：2012-03-08

申请人： Francois Hebert

发明人： Francois Hebert

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H02M7/00

CPC分类号： H01L27/088 ,  H01L21/26513 ,  H01L21/823437 ,  H01L21/823487 ,  H01L23/535 ,  H01L23/62 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/30107 ,  H01L2924/3025 ,  H02M7/003 ,  H01L2924/00

摘要： A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

摘要翻译： 电压转换器包括具有可以形成在单个管芯（“PowerDie”）上的高侧器件和低侧器件的输出电路。 高侧器件可以包括横向扩散金属氧化物半导体（LDMOS），而低侧器件可以包括沟槽栅极垂直扩散金属氧化物半导体（VDMOS）。 电压转换器还可以包括在不同管芯上的控制器电路，其可以电耦合到输出电路并与输出电路共同封装。

公开(公告)号：US09209118B2

公开(公告)日：2015-12-08

申请号：US14658479

申请日：2015-03-16

申请人： NXP B.V.

发明人： Vittorio Cuoco ,  Albert van Zuijlen ,  Josephus van der Zanden

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L23/13 ,  H01L23/36 ,  H01L23/492 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit arrangement comprising a substrate and a flange disposed on top of the substrate. The flange comprises a cantilever portion configured to project over the substrate. A die disposed on top of the flange. A first output terminal disposed on the substrate. A first lead configured to provide for an electrical connection between the die and the first output terminal. A first electrically conducting member configured to provide at least part of a current return path between the substrate and the die and arranged to bridge a gap between the cantilever portion and the substrate. The first electrically conducting member is disposed between the die and the first output terminal and is configured to enable electrical current to flow from the substrate to the cantilever portion of the flange.

摘要翻译： 一种集成电路装置，包括衬底和布置在衬底顶部上的凸缘。 凸缘包括构造成突出在基板上的悬臂部分。 设置在凸缘顶部的模具。 布置在基板上的第一输出端子。 第一引线，被配置为提供管芯和第一输出端子之间的电连接。 第一导电构件，其构造成在所述基板和所述管芯之间提供至少一部分电流返回路径，并布置成桥接所述悬臂部分和所述基板之间的间隙。 第一导电构件设置在管芯和第一输出端子之间，并且构造成使得电流能够从衬底流到凸缘的悬臂部分。

公开(公告)号：US09209117B2

公开(公告)日：2015-12-08

申请号：US14288415

申请日：2014-05-28

申请人： Jiangsu Changjiang Electronics Technology Co., Ltd.

发明人： Xinchao Wang ,  Zhizhong Liang

IPC分类号： H01L21/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/4952 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48163 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/0781 ,  H01L2224/45101 ,  H01L2224/85 ,  H01L2924/00012

摘要： A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of I/O pads formed on the metal substrate, and extending to the proximity of the die. The no-exposed-pad QFN packaging structure also includes a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process. Further, the no-exposed-pad QFN packaging structure includes metal wires connecting the die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads.

摘要翻译： 四边形无引线（QFN）封装结构。 所述QFN封装结构包括金属基板，耦合到所述金属基板的顶表面的第一裸片以及形成在所述金属基板上并延伸到所述裸片附近的多个I / O焊盘。 无裸露焊盘QFN封装结构还包括第一金属层，其包含多个对应于多个I / O焊盘并且延伸到裸片附近的内引线，并且通过多层电气形成在金属基板上 电镀工艺。 此外，无裸露焊盘QFN封装结构包括连接管芯和多个内部引线的金属线，以及形成在多个I / O焊盘的背面上的第二金属层。

公开(公告)号：US09191072B2

公开(公告)日：2015-11-17

申请号：US13415693

申请日：2012-03-08

申请人： Alessandro Finocchiaro ,  Giovanni Girlando ,  Giuseppe Palmisano ,  Giuseppe Ferla ,  Alberto Pagani

发明人： Alessandro Finocchiaro ,  Giovanni Girlando ,  Giuseppe Palmisano ,  Giuseppe Ferla ,  Alberto Pagani

IPC分类号： G08B13/14 ,  H04B5/00 ,  H01L23/66 ,  H01L25/065 ,  H01L23/00

CPC分类号： H04B5/00 ,  H01L23/66 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/48091 ,  H01L2225/06531 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0081 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.