公开(公告)号：US20160218196A1

公开(公告)日：2016-07-28

申请号：US15093557

申请日：2016-04-07

申请人： Vishay-Siliconix

发明人： Wenjie Zhang ,  Madhur Bobde ,  Qufei Chen ,  Kyle Terrill

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/06

CPC分类号： H01L29/781 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66492 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/7835

摘要： A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

公开(公告)号：US20160211320A1

公开(公告)日：2016-07-21

申请号：US14988507

申请日：2016-01-05

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Li LIU ,  Xianyong PU ,  Guangli YANG ,  Gangning WANG ,  ChiChung TAI ,  Hong SUN

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10

CPC分类号： H01L29/0847 ,  H01L21/76229 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.

摘要翻译： 半导体器件可以包括以下元件：第一掺杂部分; 第二掺杂部分; 封闭构件，其包围第一掺杂部分和第二掺杂部分; 直接接触第一掺杂部分的第一屏障; 直接接触第二掺杂部分的第二阻挡层; 电介质构件，其位于所述第一屏障和所述第二屏障之间，并且直接接触所述第一屏障和所述第二屏障中的每一个; 直接接触第一掺杂部分的第三阻挡层; 以及器件部件，其中所述器件部件的一部分位于所述电介质部件和所述第三屏障之间。

公开(公告)号：US09397211B2

公开(公告)日：2016-07-19

申请号：US14559239

申请日：2014-12-03

申请人： Texas Instruments Incorporated

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L21/324 ,  H01L21/225 ,  H01L21/761 ,  H01L21/266 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/0634 ,  H01L21/225 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7823 ,  H01L29/7835

摘要： An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

摘要翻译： 一种集成电路，其包含延伸漏极MOS晶体管，其具有漂移层，在上部RESURF层上并接触漂移层的上表面，以及在漂移层下面的埋入漏极延伸层，该漏极延伸层与漏极的漂移层电连接 在通道端处与漂移层分离。 可以在通道端处的漂移层和埋漏极延伸部之间形成较低的RESURF层。 上部RESURF层，漂移层，下部RESURF层和掩埋漏极延伸中的任何一个可以具有从漏极端到沟道端的渐变掺杂密度。 形成包含具有漂移层的延伸漏极MOS晶体管的集成电路的工艺，上部RESURF层和掩埋漏极延伸。

公开(公告)号：US09385185B2

公开(公告)日：2016-07-05

申请号：US14705050

申请日：2015-05-06

申请人： Samsung Electronics Co., Ltd.

发明人： Hoon Chang ,  Dong-Eun Jang

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417

CPC分类号： H01L29/0619 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0921 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/7816 ,  H01L29/7835 ,  H03K17/687

摘要： Semiconductor devices are provided. The semiconductor devices may include a substrate and a transistor on the substrate. The semiconductor devices may include a first guard ring of first conductivity type in the substrate adjacent the transistor. The semiconductor devices may include a second guard ring of second conductivity type opposite the first conductivity type in the substrate adjacent the first guard ring. Related semiconductor systems are also provided.

公开(公告)号：US20160190310A1

公开(公告)日：2016-06-30

申请号：US14978267

申请日：2015-12-22

申请人： SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION

发明人： Han Yu ,  Zhengliang Zhou ,  Xi Chen

IPC分类号： H01L29/78 ,  H01L23/66 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L23/66 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A radio frequency LDMOS device, wherein the drift region includes a first injection region and a second injection region; the first injection region situated between a second lateral surface of a polysilicon gate and a second lateral surface of a first Faraday shielding layer; the second injection region situated between the second lateral surface of the first Faraday shielding layer and the drain region and encloses the drain region; the second lateral surface of the second Faraday shielding layer is a surface of a side near the drain region, the maximum electric field strength of the drift region on the bottom of the second lateral surface of the second Faraday shielding layer is regulated via regulation of the doping concentration of the second injection region; the doping concentration of the first injection region is higher than the second injection region.

摘要翻译： 一种射频LDMOS器件，其中所述漂移区包括第一注入区和第二注入区; 位于多晶硅栅极的第二侧表面和第一法拉第屏蔽层的第二侧表面之间的第一注入区域; 所述第二注入区域位于所述第一法拉第屏蔽层的所述第二侧表面和所述漏极区域之间并且包围所述漏极区域; 第二法拉第屏蔽层的第二侧表面是靠近漏区的一侧的表面，通过调节第二法拉第屏蔽层的第二侧面的底部的漂移区的最大电场强度来调节 第二注入区域的掺杂浓度; 第一注入区域的掺杂浓度高于第二注入区域。

公开(公告)号：US09362118B2

公开(公告)日：2016-06-07

申请号：US14812082

申请日：2015-07-29

申请人： FUJI ELECTRIC CO., LTD.

发明人： Yoshiaki Toyoda ,  Akio Kitamura

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/761 ,  H01L21/22 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7803 ,  H01L21/02664 ,  H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

摘要： A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n−semiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer (3) of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.

摘要翻译： 垂直超结MOSFET和横向MOSFET集成在同一半导体衬底上。 横向MOSFET通过n掩埋隔离层和n扩散隔离层与垂直超结MOSFET电隔离。 横向MOSFET由形成在由n掩埋隔离层和n扩散隔离层限定的n半导体层中的p阱区域，形成在p阱区域中的n源极区域和n - 漏极区域形成 以及覆盖由n源极区域和n - 漏极区域夹持的p阱区域的一部分的栅极电极。 由于在垂直超结MOSFET的n层（3）的同时形成n埋式隔离层，因此可以降低成本。 此外，可以抑制具有n埋层隔离层的元件之间的寄生作用。

公开(公告)号：US09349818B2

公开(公告)日：2016-05-24

申请号：US14519153

申请日：2014-10-21

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/66545 ,  H01L21/76895 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

摘要： A MOS transistor device includes a substrate including a gate formed thereon, and a spacer being formed on a sidewall of the gate; a source region and a drain region formed in the substrate; and at least a first dummy contact formed above the substrate on a drain side of the gate. More important, the first dummy contact is formed apart from a surface of the substrate.

摘要翻译： MOS晶体管器件包括其上形成有栅极的衬底和形成在栅极的侧壁上的间隔物; 形成在所述基板中的源极区域和漏极区域; 以及形成在栅极的漏极侧的衬底上方的至少第一虚拟接触。 更重要的是，第一虚拟接触件与衬底的表面分开形成。

公开(公告)号：US20160141365A1

公开(公告)日：2016-05-19

申请号：US14882809

申请日：2015-10-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John B. CAMPI, JR. ,  Robert J. GAUTHIER, JR. ,  Rahul MISHRA ,  Souvick MITRA ,  Mujahid MUHAMMAD

IPC分类号： H01L29/08 ,  H01L29/78

CPC分类号： H01L29/7856 ,  B29C37/0025 ,  B29C47/065 ,  B29C47/56 ,  B29K2023/12 ,  B29K2105/16 ,  B29K2507/04 ,  B29K2995/0005 ,  B29K2995/0007 ,  B29L2009/003 ,  B29L2009/005 ,  B29L2031/34 ,  B32B3/08 ,  B32B7/02 ,  B32B27/00 ,  B32B27/08 ,  B32B27/28 ,  B32B27/306 ,  B32B27/308 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B2262/106 ,  B32B2264/105 ,  B32B2264/12 ,  B32B2270/00 ,  B32B2274/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/206 ,  B32B2307/518 ,  B32B2307/732 ,  B32B2457/16 ,  H01G4/005 ,  H01G4/14 ,  H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7851 ,  H01L2029/7858

摘要： A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

摘要翻译： 公开了一种围绕翅片双扩散金属氧化物半导体（DMOS）的器件和制造方法。 该方法包括从衬底形成多个翅片结构。 该方法还包括在衬底内形成第一导电类型和第二导电类型的阱以及多个翅片结构中相应的翅片结构。 该方法还包括在第一鳍片结构的暴露部分上形成源极接触。 该方法还包括在相邻鳍片结构的暴露部分上形成到第一鳍片结构的漏极接触。 该方法还包括在介电填充材料周围形成围绕第一鳍结构并在第一导电类型的阱上延伸的栅极结构。

公开(公告)号：US09337331B2

公开(公告)日：2016-05-10

申请号：US14826884

申请日：2015-08-14

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kanako Komatsu ,  Mariko Shimizu ,  Jun Morioka ,  Keita Takahashi ,  Masahito Nishigoori

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088 ,  H01L29/08

CPC分类号： H01L29/7816 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/7835

摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type provided on part of the first semiconductor layer in each of a first region and a second region separated from each other. A first distance is a distance between both ends of the first insulating film in a direction connecting the fourth semiconductor layer and the sixth semiconductor layer. The first distance in the first region is longer than the first distance in the second region. A second distance is a distance between the third semiconductor layer and the seventh semiconductor layer. The second distance in the first region is longer than the second distance in the second region.

摘要翻译： 半导体器件包括第一导电类型的第一半导体层和设置在彼此分离的第一区域和第二区域中的每一个中的第一半导体层的一部分上的第二导电类型的第二半导体层。 第一距离是在连接第四半导体层和第六半导体层的方向上的第一绝缘膜的两端之间的距离。 第一区域中的第一距离比第二区域中的第一距离长。 第二距离是第三半导体层和第七半导体层之间的距离。 第一区域中的第二距离比第二区域中的第二距离长。

公开(公告)号：US09324711B2

公开(公告)日：2016-04-26

申请号：US14315898

申请日：2014-06-26

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Taiji Ema ,  Kazushi Fujita

IPC分类号： H01L23/62 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/7833

摘要： A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region. A second transistor includes a second impurity layer of the first conduction type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and being thinner than the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer, a second gate electrode formed above the second gate insulating film, and second source/drain regions of the second conduction type formed in the second epitaxial semiconductor layer and in the semiconductor substrate in the second region.

摘要翻译： 第一晶体管包括形成在半导体衬底的第一区域中的第一导电类型的第一杂质层，形成在第一杂质层上方的第一外延半导体层，形成在第一外延半导体层上方的第一栅极绝缘膜， 形成在第一栅极绝缘膜上方的栅极电极和形成在第一外延半导体层中的第二导电类型的第一源极/漏极区域和在第一区域中的半导体衬底中。 第二晶体管包括形成在半导体衬底的第二区域中的第一导电类型的第二杂质层，形成在第二杂质层上方并且比第一外延半导体层薄的第二外延半导体层，形成第二栅极绝缘膜 在第二外延半导体层上方形成第二栅极，形成在第二栅极绝缘膜上方的第二栅极电极以及形成在第二外延半导体层中的第二导电类型的第二源极/漏极区域和在第二区域中的半导体衬底中。