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    Semiconductor device having depletion region for improving breakdown voltage characteristics
    2.
    发明授权
    Semiconductor device having depletion region for improving breakdown voltage characteristics 有权
    具有用于改善击穿电压特性的耗尽区的半导体器件

    公开(公告)号：US09397231B2

    公开(公告)日：2016-07-19

    申请号：US14337811

    申请日：2014-07-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Ju Kim ,  Jae-June Jang ,  Hoon Chang ,  Jae-Ho Kim ,  Kyu-Heon Cho

    IPC: H01L29/872 ,  H01L29/36 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/36 ,  H01L29/66143

    Abstract: A semiconductor device having a wide depletion region for increasing the breakdown voltage of the device includes an epitaxial layer of a first conductive type. An anode electrode and a cathode electrode are arranged on the epitaxial layer to be separated from each other. A first drift layer of the first conductive type formed in the epitaxial layer. A Schottky contact area is at a region of contact between the anode electrode and the first drift layer. An impurity region of a second conductive type is different from the first conductive type at the epitaxial layer. An insular impurity region is formed below the Schottky contact area.

    Abstract translation: 具有用于增加器件的击穿电压的宽耗尽区的半导体器件包括第一导电类型的外延层。 阳极电极和阴极电极布置在外延层上以彼此分离。 第一导电类型的第一漂移层形成在外延层中。 肖特基接触区域位于阳极电极和第一漂移层之间的接触区域。 第二导电类型的杂质区域与外延层处的第一导电类型不同。 在肖特基接触区域下面形成一个杂质区域。

    Semiconductor device having power metal-oxide-semiconductor transistor
    5.
    发明授权
    Semiconductor device having power metal-oxide-semiconductor transistor 有权
    具有功率金属氧化物半导体晶体管的半导体器件

    公开(公告)号：US09245995B2

    公开(公告)日：2016-01-26

    申请号：US13921412

    申请日：2013-06-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae-june Jang ,  Kyu-heon Cho ,  Min-hwan Kim ,  Dong-eun Jang ,  Hoon Chang

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L29/08

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66681

    Abstract: A semiconductor device includes a power metal-oxide-semiconductor (MOS) transistor including a semiconductor substrate, an impurity region on the semiconductor substrate, the impurity region having a first conductivity, a drift region in the impurity region, the drift region having the first conductivity, a body region in the impurity region adjacent to the drift region, the body region having a second conductivity different from the first conductivity, a drain extension insulating layer on the drift region, a gate insulating layer and a gate electrode sequentially stacked across a portion of the body region and a portion of the drift region, a drain extension electrode on the drain extension insulating layer, a drain region contacting a side of the drift region opposite to the body region, the drain region having the first conductivity, and a source region in the body region, the source region having the second conductivity.

    Abstract translation: 半导体器件包括：包含半导体衬底的功率金属氧化物半导体（MOS）晶体管，半导体衬底上的杂质区域，具有第一导电性的杂质区域，杂质区域中的漂移区域，具有第一 电导率，与漂移区相邻的杂质区域中的体区，具有不同于第一导电性的第二电导率的体区，漂移区上的漏极延伸绝缘层，顺序地层叠在栅极绝缘层上的栅电极 所述体区的一部分和所述漂移区的一部分，所述漏极延伸绝缘层上的漏极延伸电极，与所述体区的相反侧的所述漂移区的漏极区域，所述漏极区具有所述第一导电性，以及 源区域，源区域具有第二导电性。

    Metal oxide semiconductor devices with multiple drift regions
    6.
    发明授权
    Metal oxide semiconductor devices with multiple drift regions 有权
    具有多个漂移区域的金属氧化物半导体器件

    公开(公告)号：US08975693B2

    公开(公告)日：2015-03-10

    申请号：US13683505

    申请日：2012-11-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eung-Kyu Lee ,  Jae-June Jang ,  Hoon Chang ,  Min-Hwan Kim ,  Sung-Ryoul Bae ,  Dong-Eun Jang

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66681

    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a buried layer a second conductivity type different from the first conductivity type on the substrate and an epitaxial layer of the second conductivity type on the buried layer. The device further includes a pocket well of the first conductivity type in the epitaxial layer, a first drift region in the epitaxial layer at least partially overlapping the pocket well, a second drift region in the epitaxial layer and spaced apart from the first drift region, and a body region of the first conductivity type in the pocket well. A gate electrode is disposed on the body region, the pocket well and the first drift region and has an edge overlying the epitaxial region between the first and second drift regions.

    Abstract translation: 半导体器件包括第一导电类型的半导体衬底，与衬底上的第一导电类型不同的第二导电类型的掩埋层和在掩埋层上的第二导电类型的外延层。 器件还包括在外延层中的第一导电类型的凹穴，外延层中的至少部分地与凹穴阱重叠的第一漂移区，外延层中的与第一漂移区间隔开的第二漂移区， 以及口袋中的第一导电类型的体区。 栅电极设置在体区，口腔和第一漂移区上，并且具有覆盖第一和第二漂移区之间的外延区的边缘。

    METAL OXIDE SEMICONDUCTOR DEVICES WITH MULTIPLE DRIFT REGIONS
    7.
    发明申请
    METAL OXIDE SEMICONDUCTOR DEVICES WITH MULTIPLE DRIFT REGIONS 有权
    具有多个DRIFT区域的金属氧化物半导体器件

    公开(公告)号：US20130256794A1

    公开(公告)日：2013-10-03

    申请号：US13683505

    申请日：2012-11-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eung-Kyu Lee ,  Jae-June Jang ,  Hoon Chang ,  Min-Hwan Kim ,  Sung-Ryoul Bae ,  Dong-Eun Jang

    IPC: H01L29/78

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66681

    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a buried layer a second conductivity type different from the first conductivity type on the substrate and an epitaxial layer of the second conductivity type on the buried layer. The device further includes a pocket well of the first conductivity type in the epitaxial layer, a first drift region in the epitaxial layer at least partially overlapping the pocket well, a second drift region in the epitaxial layer and spaced apart from the first drift region, and a body region of the first conductivity type in the pocket well. A gate electrode is disposed on the body region, the pocket well and the first drift region and has an edge overlying the epitaxial region between the first and second drift regions.

    Abstract translation: 半导体器件包括第一导电类型的半导体衬底，与衬底上的第一导电类型不同的第二导电类型的掩埋层和在掩埋层上的第二导电类型的外延层。 器件还包括在外延层中的第一导电类型的凹穴，外延层中的至少部分地与凹穴阱重叠的第一漂移区，外延层中的与第一漂移区间隔开的第二漂移区， 以及口袋中的第一导电类型的体区。 栅电极设置在体区，口腔和第一漂移区上，并且具有覆盖第一和第二漂移区之间的外延区的边缘。

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