公开(公告)号：US20160218046A1

公开(公告)日：2016-07-28

申请号：US15089394

申请日：2016-04-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L23/34 ,  H01L23/522 ,  H01L27/06 ,  H03K3/037

CPC classification number: H01L27/0688 ,  H01L23/3677 ,  H01L23/5226 ,  H01L23/5252 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K3/0375 ,  H03K19/096 ,  H03K19/1774 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the device includes a Phase Lock Loop (“PLL”) circuit, where the second clock distribution structure is connected to the Phase Lock Loop (“PLL”) circuit, and where the second transistors are aligned to the first transistors with less than 200 nm alignment error.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，所述第二晶体管覆盖所述第一互连层，其中所述第一层包括第一时钟分配结构，其中所述第二层包括第二时钟分配结构，其中所述器件包括锁相环（“PLL” “）电路，其中第二时钟分配结构连接到锁相环（”PLL“）电路，并且其中第二晶体管与具有小于200nm对准误差的第一晶体管对准。

公开(公告)号：US09397665B2

公开(公告)日：2016-07-19

申请号：US14462404

申请日：2014-08-18

Applicant: Callahan Cellular, L.L.C.

Inventor： Raminda Udaya Madurawe

IPC: H03K19/177 ,  H03K19/173 ,  H01L27/02 ,  H01L27/118 ,  H01L27/12 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11

CPC classification number: H03K19/1735 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/11803 ,  H01L27/11898 ,  H01L27/1203 ,  H01L2924/0002 ,  H03K19/1733 ,  H03K19/17728 ,  H03K19/1776 ,  H01L2924/00

Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

Abstract translation: 可编程半导体器件包括用户可编程开关，其包括位于沉积在衬底层上的晶体管材料层上方的可配置元件。

公开(公告)号：US20160163642A1

公开(公告)日：2016-06-09

申请号：US14876009

申请日：2015-10-06

Applicant: International Business Machines Corporation

Inventor： Toshiaki Kirihata ,  Edward P. Maciejewski ,  Subramanian S. Iyer ,  Chengwen Pei ,  Deepal U. Wehella-Gamage

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/76886 ,  H01L21/84 ,  H01L23/525 ,  H01L23/5252 ,  H01L23/535 ,  H01L27/11206 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged.

公开(公告)号：US09350356B2

公开(公告)日：2016-05-24

申请号：US14842195

申请日：2015-09-01

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kosuke Tatsumura ,  Masato Oda ,  Koichiro Zaitsu ,  Shinichi Yasuda

IPC: H03K19/177 ,  H01L25/00 ,  H03K17/22 ,  B82Y10/00 ,  H03K3/356 ,  H03K3/037 ,  H01L23/525 ,  H01L23/00 ,  H01L25/065 ,  H01L27/092 ,  H01L27/105

CPC classification number: H03K19/17728 ,  B82Y10/00 ,  G11C8/10 ,  G11C8/12 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/77 ,  G11C2213/79 ,  H01L23/5252 ,  H01L24/45 ,  H01L25/0655 ,  H01L27/092 ,  H01L27/101 ,  H01L27/105 ,  H01L27/2463 ,  H01L2924/00014 ,  H01L2924/13091 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/356182 ,  H03K17/223 ,  H03K19/17748 ,  H03K19/1776 ,  H01L2924/00 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: According to one embodiment, a reconfigurable circuit includes first, second, third and fourth circuit blocks arranged with a matrix, a first conductive line shared by the first and second circuit blocks, a second conductive line shared by the third and fourth circuit blocks, a third conductive line shared by the first and third circuit blocks, the third conductive line crossing the first and second conductive lines, a fourth conductive line shared by the second and fourth circuit blocks, the fourth conductive line crossing the first and second conductive lines, a first controller controlling voltages to be applied to the first and second conductive lines, and a second controller controlling voltages to be applied to the third and fourth conductive lines.

Abstract translation: 根据一个实施例，可重构电路包括布置有矩阵的第一，第二，第三和第四电路块，由第一和第二电路块共享的第一导线，由第三和第四电路块共享的第二导线， 由第一和第三电路块共享的第三导线，与第一和第二导线交叉的第三导线，由第二和第四电路块共享的第四导线，与第一和第二导线交叉的第四导线， 控制施加到第一和第二导线的电压的第一控制器，以及控制施加到第三和第四导线的电压的第二控制器。

公开(公告)号：US09318408B2

公开(公告)日：2016-04-19

申请号：US14828517

申请日：2015-08-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/00 ,  H01L23/34 ,  H01L27/06 ,  H01L23/522 ,  H01L23/50

CPC classification number: H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L27/0688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H03K19/096 ,  H03K19/1774 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the second clock distribution structure is connected to the first clock distribution structure with a plurality of through layer vias, and where the second transistors are aligned to the first transistors with less than 100 nm alignment error.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，覆盖第一层互连层的第二晶体管，其中第一层包括第一时钟分配结构，其中第二层包括第二时钟分配结构，其中第二时钟分配结构连接到第一层 具有多个贯通层通孔的时钟分配结构，并且其中第二晶体管与具有小于100nm对准误差的第一晶体管对准。

公开(公告)号：US09312009B2

公开(公告)日：2016-04-12

申请号：US14592477

申请日：2015-01-08

Applicant: eMemory Technology Inc.

Inventor： Tzu-Neng Lai ,  Chih-Hao Huang

IPC: G11C7/00 ,  G11C16/08 ,  G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  G11C16/10 ,  G11C16/26 ,  G11C17/04 ,  G11C17/08 ,  H01L23/528 ,  H01L27/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/93 ,  H01L27/115 ,  H03K3/356 ,  H01L23/525

CPC classification number: G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C17/04 ,  G11C17/08 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/76 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/11206 ,  H01L27/11524 ,  H01L29/1079 ,  H01L29/4916 ,  H01L29/93 ,  H01L2924/0002 ,  H03K3/356182 ,  H01L2924/00

Abstract: A non-volatile memory includes a memory array, a row decoder, a column decoder, a write buffer and a sensing circuit. The column decoder includes a programming decoder and a reading decoder. The programming decoder is connected with n bit lines of the memory array. The reading decoder is connected with the n bit lines. During a program cycle, a programming control signal set is activated. Consequently, the programming decoder determines a selected memory cell, and a cell current generated by the selected memory cell flows to the write buffer through the programming decoder and a programming data line. During a read cycle, a reading control signal set is activated. Consequently, the reading decoder determines the selected memory cell, and the cell current generated by the selected memory cell flows to the sensing circuit through the reading decoder and a reading data line.

Abstract translation: 非易失性存储器包括存储器阵列，行解码器，列解码器，写缓冲器和感测电路。 列解码器包括编程解码器和读取解码器。 编程解码器与存储器阵列的n位线连接。 读取解码器与n位线连接。 在编程周期中，编程控制信号组被激活。 因此，编程解码器确定所选择的存储单元，并且由所选择的存储器单元产生的单元电流通过编程解码器和编程数据线流向写入缓冲器。 在读取周期期间，读取控制信号组被激活。 因此，读取解码器确定所选择的存储单元，并且由选择的存储单元产生的单元电流通过读取解码器和读取数据线流到感测电路。

公开(公告)号：US09305786B2

公开(公告)日：2016-04-05

申请号：US14633747

申请日：2015-02-27

Applicant: SK hynix Inc.

Inventor： Yong Sun Jung

IPC: H01L21/28 ,  H01L21/283 ,  H01L27/108 ,  H01L27/088 ,  H01L23/525

CPC classification number: H01L21/28008 ,  H01L21/283 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/108 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device using a small-sized metal contact as a program gate of an antifuse, and a method of fabricating the same are described. The semiconductor device includes a metal contact structure formed on a semiconductor substrate of a peripheral circuit area, and includes a first gate insulating layer to be ruptured. A gate structure is formed on the semiconductor substrate to one side of the metal contact structure.

公开(公告)号：US09287274B2

公开(公告)日：2016-03-15

申请号：US14608141

申请日：2015-01-28

Applicant: SK hynix Inc.

Inventor： Yeong Eui Hong

IPC: H01L27/112 ,  H01L21/266 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L23/525 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11206 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/266 ,  H01L21/28017 ,  H01L21/31105 ,  H01L23/5252 ,  H01L29/66409 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antifuse of a semiconductor device and a method of fabricating the same capable of causing an antifuse to stably operate by rupturing the antifuse at a specific point and stabilizing a current level when rupturing the antifuse are provided. The antifuse may include: a device isolation layer defining a first active region in a semiconductor substrate; a first and second junction regions provided in the first active region; a second active region formed over the first junction region; a gate insulating layer formed over the first active region and the second active region; and a gate electrode formed over the gate insulating layer.

公开(公告)号：US09281074B2

公开(公告)日：2016-03-08

申请号：US14222684

申请日：2014-03-24

Applicant: eMemory Technology Inc.

Inventor： Meng-Yi Wu ,  Chih-Hao Huang ,  Hsin-Ming Chen

IPC: G11C17/16 ,  H01L27/10 ,  H01L27/112 ,  G11C17/18 ,  H01L29/78 ,  H01L23/525

CPC classification number: G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/11206 ,  H01L27/11286 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.

公开(公告)号：US20160064326A1

公开(公告)日：2016-03-03

申请号：US14937812

申请日：2015-11-10

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Yiheng Xu ,  Lawrence A. Clevenger ,  Carl Radens ,  Edem Wornyo

IPC: H01L23/525 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01F17/0006 ,  H01F17/02 ,  H01F2017/0073 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/5252 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.