公开(公告)号：US20200020688A1

公开(公告)日：2020-01-16

申请号：US16034703

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Kern Rim

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/027 ,  H01L21/3213 ,  H01L27/02

Abstract: Integrated circuits employing varied gate topography between an active gate region(s) and a field gate region(s) in a gate(s) for reduced gate layout parasitic capacitance, and related methods, are disclosed. In exemplary aspects, the gate topography (e.g., height) of a gate in a circuit cell used to form gates for devices formed therein to form an integrated circuit is varied between an active gate and a field gate(s) of the gate. In this manner, the overall volume of material in the gate can be reduced due to the reduction in volume of the field gate(s) to reduce gate layout parasitic capacitance. Reducing gate layout parasitic capacitance in a circuit cell can reduce the overall parasitic capacitance of an integrated circuit formed from the circuit cell to achieve the desired integrated circuit delay performance.

公开(公告)号：US20190319022A1

公开(公告)日：2019-10-17

申请号：US15952638

申请日：2018-04-13

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  John Jianhong Zhu ,  Da Yang

IPC: H01L27/02 ,  H01L27/118 ,  H03K3/3562 ,  H01L23/48

Abstract: Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections. In exemplary aspects disclosed herein, to allow cross-connections to be made across different gates between PMOS and NMOS transistors formed in the circuit cell, cut areas in the circuit cell are located in different horizontal routing tracks and offset from each other in the direction of longitudinal axes of gates. Gate cross-connections can be routed around offset gate cut areas and coupled to active gates to form gate cross-connections. In this manner, fewer metal layers may be required to provide such cross-connections in the circuit cell, thus reducing area. Further, gate contacts of cross-connected gates can be formed as gate contacts over active areas (GCOAs) in diffusion areas of the circuit cell, thus facilitating easier routing of interconnections in non-diffusion area of the circuit cell for further ease of routing.

公开(公告)号：US10134734B2

公开(公告)日：2018-11-20

申请号：US15197949

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Yanxiang Liu ,  Kern Rim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/49

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

公开(公告)号：US10018515B2

公开(公告)日：2018-07-10

申请号：US14856004

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Kern Rim

IPC: G01K7/01 ,  H01L27/092 ,  H01L29/786

CPC classification number: G01K7/015 ,  H01L27/0251 ,  H01L27/0924 ,  H01L29/78606

Abstract: A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).

公开(公告)号：US09876017B2

公开(公告)日：2018-01-23

申请号：US14559258

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  G11C5/06 ,  G11C8/14 ,  G11C11/418 ,  G11C11/412 ,  G11C8/16 ,  H01L21/768

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.

公开(公告)号：US20170207313A1

公开(公告)日：2017-07-20

申请号：US15213879

申请日：2016-07-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  Peijie Feng ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure employing recessed conductive structures for conductively coupling nanowire structures are disclosed. Conductive structures are disposed between adjacent nanowire structures to conductively couple nanowire structures. Providing conductive structures in the nanowire channel structure increases the average cross-sectional area of nanowire structures, as compared to a similar nanowire channel structure not employing conductive structures, thus increasing effective channel width and drive strength for a given channel structure height. The precision of a gate material filling process is also eased, because gate material does not have to be disposed in areas between adjacent nanowire structures occupied by conductive structures. The conductive structure width can also be recessed with regard to width of nanowire structures in the nanowire channel structure to allow for a thicker metal gate to lower the gate resistance, while providing excellent electrostatic gate control of the channel.

公开(公告)号：US09653399B2

公开(公告)日：2017-05-16

申请号：US14622516

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Da Yang ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/52 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/02178 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/535

Abstract: An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).

公开(公告)号：US20160293485A1

公开(公告)日：2016-10-06

申请号：US14853670

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu ,  Junjing Bao ,  Niladri Narayan Mojumder ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/535 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

Abstract translation: 翅片型半导体器件包括栅极结构和源极/漏极结构。 翅片型半导体器件还包括耦合到栅极结构的栅极硬掩模结构。 门硬掩模结构包括第一材料。 翅片型半导体器件还包括耦合到源极/漏极结构的源极/漏极硬掩模结构。 源极/漏极硬掩模结构包括第二材料。

公开(公告)号：US20160086805A1

公开(公告)日：2016-03-24

申请号：US14626293

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Zhongze Wang ,  Kern Rim ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/28 ,  H01L21/306 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28079 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A particular semiconductor device includes a substrate, a source contact, a drain contact, and a metal-gate. The substrate includes a source region, a drain region, and a channel. The source contact is coupled to the source region. The drain contact is coupled to the drain region. The metal-gate is coupled to the channel. The metal-gate includes an amorphous metal layer.

Abstract translation: 特定的半导体器件包括衬底，源极接触，漏极接触和金属栅极。 衬底包括源极区，漏极区和沟道。 源极触点耦合到源极区域。 漏极触点耦合到漏极区域。 金属栅极耦合到通道。 金属栅极包括非晶金属层。