公开(公告)号：US09871121B2

公开(公告)日：2018-01-16

申请号：US14341568

申请日：2014-07-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US09859210B2

公开(公告)日：2018-01-02

申请号：US14744912

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Da Yang

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/092 ,  H01L27/12 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L23/48 ,  H01L23/525

CPC classification number: H01L23/528 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211

Abstract: In a particular aspect, an integrated circuit includes a first transistor including a first source region and a first drain region. The integrated circuit includes a second transistor including a second source region and a second drain region. The integrated circuit includes a first gate structure coupled to the first transistor and to the second transistor. The first gate structure is included in a first layer. The integrated circuit further includes a first metal line coupled to the first source region and to the second drain region. The first metal line has a two-dimensional routing arrangement and is included in a second layer that is distinct from the first layer.

公开(公告)号：US20170338215A1

公开(公告)日：2017-11-23

申请号：US15160992

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Giridhar Nallapati ,  Da Yang ,  Kern Rim ,  Robert Bucki ,  Choh Fei Yeap

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/11803 ,  H01L28/00 ,  H01L2027/11809 ,  H01L2027/11824 ,  H01L2027/11874 ,  H01L2027/11881

Abstract: A heterogeneous cell array includes a first column of cells and a second column of cells. The first column of cells includes a first cell having a first area and a second cell having the first area. The first cell includes two fin-type field effect transistors having a first number of fins and the second cell includes two fin-type field effect transistors having the first number of fins. The second column of cells includes a third cell having a second area. The third cell is adjacent to the first cell and to the second cell, and the third cell includes two fin-type field effect transistors having a second number of fins. The second area is greater than the first area, and the second number of fins is greater than the first number of fins.

公开(公告)号：US09824936B2

公开(公告)日：2017-11-21

申请号：US15293213

申请日：2016-10-13

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L21/321 ,  H01L21/3213 ,  B82Y10/00 ,  H01L27/088

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

公开(公告)号：US09698232B2

公开(公告)日：2017-07-04

申请号：US14661953

申请日：2015-03-18

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Stanley Seungchul Song

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4958 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/32133 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/53238 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66568 ,  H01L29/78

Abstract: A semiconductor device includes a gate region, a conductive cap, and an interconnect. The gate region (e.g., a metal-gate transistor) includes a metal gate region and a high dielectric constant (high-K) gate dielectric region. The conductive cap is disposed on a surface of the metal gate region and on a surface of the high-K gate dielectric region, and the interconnect is disposed on the conductive cap. The conductive cap includes a conductive material that electrically connects the gate region to the interconnect.

公开(公告)号：US20170186846A1

公开(公告)日：2017-06-29

申请号：US14980850

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7831

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

公开(公告)号：US09620454B2

公开(公告)日：2017-04-11

申请号：US14484366

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Kern Rim ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Da Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L23/53257 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes.

公开(公告)号：US20170092587A1

公开(公告)日：2017-03-30

申请号：US15378633

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Junjing Bao ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Niladri Narayan Mojumder ,  Choh Fei Yeap

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53223 ,  B29C64/386 ,  B33Y50/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes an aluminum oxide barrier layer. The aluminum oxide barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

公开(公告)号：US09594864B2

公开(公告)日：2017-03-14

申请号：US14693690

申请日：2015-04-22

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap

IPC: G06F17/50 ,  G03F7/20 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G03F7/70433 ,  G06F17/5068 ,  G06F17/5081 ,  H01L27/0207

Abstract: A circuit layout data has a start value of a first-axis pitch and a start value of a second-axis pitch, the second axis pitch being transverse to the first-axis pitch. The start value of the first axis pitch and the start value of the second axis pitch correspond to single pattern lithography. The first axis pitch is scaled to a first axis single pattern-to-double pattern pitch transition threshold, and then additionally scaled until reaching a first axis double pattern resolution limit. Scaling the first axis pitch to the first axis double pattern resolution limit utilizes routing spaces parallel to the second axis pitch.

Abstract translation: 电路布局数据具有第一轴节距的起始值和第二轴节距的起始值，第二轴节距横向于第一轴节距。 第一轴距的开始值和第二轴距的开始值对应于单模式光刻。 第一轴音调被缩放到第一轴单一图案到双重图案间距转换阈值，然后另外缩放直到达到第一轴双重图案分辨率极限。 将第一轴距调整为第一轴双重图案分辨率极限利用与第二轴距平行的路线空间。

公开(公告)号：US09564518B2

公开(公告)日：2017-02-07

申请号：US14495562

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/10

CPC classification number: H01L29/66803 ,  H01L21/2254 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract translation: 体硅（Si）的一部分形成为具有翅片基底的翅片，并且在散热片基底上形成有工艺中的翅片。 翅片基底是掺杂硅，而工艺中的鳍是硅锗（SiGe）。 工艺中的SiGe鳍具有源极区和漏极区。 硼原位掺杂到漏区并进入源区。 任选地，硼通过在漏极区域和源极区域上形成具有硼的外延层进行原位掺杂，以及驱动退火以在源极区域和漏极区域中扩散硼。