公开(公告)号：US09418913B2

公开(公告)日：2016-08-16

申请号：US13682510

申请日：2012-11-20

Applicant: STATS ChipPAC, Ltd.

Inventor： Seong Bo Shim ,  Kyung Oe Kim ,  Yong Hee Kang

IPC: H01L23/488 ,  H01L23/00 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34 ,  H01L21/50 ,  H01L23/482 ,  H01L25/10

CPC classification number: H01L23/48 ,  H01L21/4846 ,  H01L21/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/4824 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13016 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/8121 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/3452 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around bumps between the semiconductor die and substrate.

Abstract translation: 半导体器件具有在半导体管芯的有效表面上形成有多个凸点的半导体管芯。 具有互连位置的多个第一导电迹线形成在衬底上。 凸块比互连部位宽。 在第一导电迹线上形成表面处理。 与第一导电迹线相邻地形成多个第二导电迹线。 在第二导电迹线上形成氧化物层。 在衬底的远离互连位置的区域上形成掩模层。 这些凸块被结合到互连部位，使得凸块覆盖互连部位的顶表面和侧表面。 氧化物层保持凸块和第二导电迹线之间的电隔离。 在半导体管芯和衬底之间的凸起周围沉积密封剂。

公开(公告)号：US20160234938A1

公开(公告)日：2016-08-11

申请号：US15022805

申请日：2014-09-18

Applicant: NOVALIA LTD

Inventor： Kate STONE

IPC: H05K1/11 ,  H05K3/32 ,  H05K1/03 ,  H05K3/12 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/111 ,  C09J9/02 ,  H01L24/29 ,  H05K1/028 ,  H05K1/032 ,  H05K1/0326 ,  H05K1/0346 ,  H05K1/038 ,  H05K1/0386 ,  H05K1/189 ,  H05K3/125 ,  H05K3/1275 ,  H05K3/32 ,  H05K3/321 ,  H05K2201/0145 ,  H05K2201/0158 ,  H05K2201/0329 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2201/10727 ,  Y02P70/611

Abstract: A circuit board assembly is described. The circuit board assembly comprises a circuit board comprising a substrate supporting a plurality of contact lands and a device, such as a bare die or printed circuit board, comprising a plurality of contact pads which is mounted on the circuit board such that the contact pads are aligned with the contact lands. The circuit board assembly comprises an interconnect layer which has a sheet resistance, Rs, of at least 0.5 MΩ/sq, which is disposed between the device and the circuit board and which is arranged to provide electrical connections between the contact lands and corresponding contact pads.

Abstract translation: 描述电路板组件。 电路板组件包括电路板，其包括支撑多个接触焊盘的衬底和诸如裸芯片或印刷电路板的器件，其包括多个接触焊盘，其安装在电路板上，使得接触焊盘 与接触面对齐。 电路板组件包括互连层，其具有至少0.5MΩ/ sq的薄层电阻Rs，该电阻布置在器件和电路板之间，并且布置成提供接地焊盘与相应的接触焊盘之间的电连接 。

公开(公告)号：US20160233192A1

公开(公告)日：2016-08-11

申请号：US15042097

申请日：2016-02-11

Applicant: ENDURA TECHNOLOGIES LLC

Inventor： Taner Dosluoglu

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19103 ,  H05K1/185 ,  H05K2201/10674

Abstract: A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation.

Abstract translation: 可扩展的开关调节器架构具有集成电感器。 在一些实施例中，开关调节器的开关的面积和电流驱动能力与内置在开关上方的区域内的电感相匹配。 在一些实施例中，组合的开关和电感器被构造为单元电池，并且可以组合以形成更大的元件，用于更高的电流驱动能力和多相操作所需。

公开(公告)号：US20160233152A1

公开(公告)日：2016-08-11

申请号：US15133244

申请日：2016-04-20

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu

IPC: H01L23/495 ,  H01L21/768

CPC classification number: H01L23/49586 ,  H01L21/4828 ,  H01L21/76823 ,  H01L21/76825 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2924/181 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a metal stud array having metal studs. The selective-electroplating epoxy compound covers the metal stud array. The selective-electroplating epoxy compound includes non-conductive metal complex. The conductive vias are directly embedded in the selective electroplating epoxy compound to be respectively connected to the metal studs and extended to a top surface of the selective-electroplating epoxy compound. Each of the conductive vias includes a lower segment connected to the corresponding metal stud and an upper segment connected to the lower segment and extended to the top surface, and a smallest diameter of the upper segment is greater than a largest diameter of the lower segment. The patterned circuit layer is directly disposed on the top surface and electrically connected to the conductive vias.

Abstract translation: 封装结构包括引线框，选择性电镀环氧化合物，导电通孔和图案化电路层。 引线框架包括具有金属螺柱的金属螺柱阵列。 选择性电镀环氧化合物覆盖金属螺柱阵列。 选择性电镀环氧化合物包括非导电金属络合物。 导电通孔直接嵌入选择性电镀环氧化合物中，以分别连接到金属螺柱并延伸到选择性电镀环氧化合物的顶表面。 每个导电通孔包括连接到相应的金属螺柱的下部段和连接到下部段并延伸到顶部表面的上段，并且上段的最小直径大于下段的最大直径。 图案化电路层直接设置在顶表面上并电连接到导电通孔。

公开(公告)号：US09406532B2

公开(公告)日：2016-08-02

申请号：US14221486

申请日：2014-03-21

Applicant: Tessera, Inc.

Inventor： Belgacem Haba ,  Ilyas Mohammed

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H05K3/40

CPC classification number: H01L21/486 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K3/4046 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10674

Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.

Abstract translation: 公开了一种用于制造互连部件的方法，包括形成远离参考表面延伸的多个金属柱。 每个柱形成具有一对相对的端面和在它们之间延伸的边缘表面。 形成接触边缘表面和相邻柱之间的填充空间的电介质层。 电介质层具有邻近第一和第二端面的第一和第二相对表面。 电介质层的热膨胀系数小于8ppm /℃。互连部件完成，使得它们在横向方向上延伸的柱的第一和第二端面之间没有互连。 第一和第二多个可湿接触部分邻近第一和第二相对表面。 可湿接触可用于将互连部件连接到微电子元件或电路板。

公开(公告)号：US20160190057A1

公开(公告)日：2016-06-30

申请号：US15061747

申请日：2016-03-04

Applicant: BROADCOM CORPORATION

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/32 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L23/3142 ,  H01L23/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/186 ,  H05K3/4046 ,  H05K3/4688 ,  H05K2201/0218 ,  H05K2201/09609 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/041 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2924/00012

Abstract: Various examples are provided for interconnection structures for molded IC packages. In one example, among others, an IC package includes a substrate and an interposer. A plurality of conductive elements provide physical and electrical contact between a surface of the substrate and a surface of the interposer. A standoff element disposed between the surfaces of the substrate and interposer provides a minimum spacing between the surfaces of the substrate and interposer. In some implementations, a standoff element is disposed between an IC die disposed on the surface of the substrate and the surface of the interposer. In another example, a method includes coupling conductive elements to a surface of an interposer, attaching a standoff element, coupling the conductive elements to a surface of a substrate, and forming an embedded layer between the interposer and substrate. The standoff element defines a minimum gap between the interposer and the substrate.

Abstract translation: 为模制IC封装的互连结构提供了各种实例。 在一个示例中，其中，IC封装包括基板和插入件。 多个导电元件在基板的表面和插入件的表面之间提供物理和电接触。 设置在基板和插入件的表面之间的间隔元件在基板和插入件的表面之间提供最小的间隔。 在一些实施方案中，支架元件设置在设置在基板的表面上的IC管芯和插入件的表面之间。 在另一示例中，一种方法包括将导电元件耦合到插入件的表面，附接支座元件，将导电元件连接到基板的表面，以及在插入器和基板之间形成嵌入层。 支座元件限定了插入件和基板之间的最小间隙。

公开(公告)号：US20160183383A1

公开(公告)日：2016-06-23

申请号：US14902813

申请日：2014-06-23

Applicant: AT&S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT

Inventor： Wolfgang Schrittwieser ,  Mike Morianz ,  Alexander Kasper ,  Erich Preiner ,  Thomas Krivec

IPC: H05K3/32 ,  H05K3/00 ,  H05K1/09 ,  H05K3/46 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K3/32 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/8203 ,  H01L2224/92144 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/185 ,  H05K3/0026 ,  H05K3/02 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/0574 ,  H05K2203/1469

Abstract: A method for contacting and rewiring an electronic component embedded in a PCB in the following manner is disclosed.A first permanent resist layer is applied to one contact side of the PCB.The first permanent resist layer is structured to produce exposures in the area of contacts of the electronic component.A second permanent resist layer is applied onto the structured first permanent resist layer.The second permanent resist layer is structured to expose the exposures in the area of the contacts and to produce exposures in line with the desired conductor tracks.The exposures are chemically coated with copper the copper is electric-plated to the exposures.Excess copper in the areas between the exposures is removed.

Abstract translation: 公开了一种用于以下列方式接触和重新布线嵌入在PCB中的电子部件的方法。 将第一永久抗蚀剂层施加到PCB的一个接触侧。 第一永久抗蚀剂层被构造成在电子部件的触点区域产生曝光。 将第二永久抗蚀剂层施加到结构化的第一永久抗蚀剂层上。 第二永久抗蚀剂层被构造为暴露接触区域中的曝光并产生与所需导体轨迹一致的曝光。 曝光用铜化学涂覆，铜被电镀到曝光。 在曝光之间的区域中过多的铜被去除。

公开(公告)号：US09368467B2

公开(公告)日：2016-06-14

申请号：US13654713

申请日：2012-10-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34

CPC classification number: H01L24/16 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2924/00014 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09727 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A substrate structure is provided, including a substrate body and a plurality of circuits formed on the substrate body. At least one of the circuits has an electrical contact for connecting to an external element and the electrical contact is narrower in width than the circuit, thereby meeting the requirements of fine line/fine pitch and miniaturization, improving the product yield and reducing the fabrication cost.

Abstract translation: 提供了一种基板结构，包括基板主体和形成在基板主体上的多个电路。 至少一个电路具有用于连接到外部元件的电触点，并且电触头的宽度比电路窄，从而满足细线/细间距和小型化的要求，提高产品产量并降低制造成本 。

公开(公告)号：US09349628B2

公开(公告)日：2016-05-24

申请号：US13848549

申请日：2013-03-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei-Chin Lau ,  Hai-Wah Lim

IPC: H05K3/00 ,  H01L21/68 ,  H01L23/16 ,  H01L23/00 ,  H05K3/34

CPC classification number: H01L21/68 ,  H01L23/16 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/10 ,  H01L2224/10155 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/0008 ,  H05K3/3436 ,  H05K2201/09145 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0165 ,  H05K2203/0169 ,  H05K2203/0278 ,  H05K2203/167 ,  Y10T29/49124 ,  Y10T29/49133 ,  Y10T29/53178 ,  Y10T156/10 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods and apparatus for coupling a stiffener frame to a circuit board are disclosed. In one aspect, a method for engaging a stiffener frame and a circuit board positioned in a fixture is provided. The method includes positioning an alignment plate on the stiffener frame, such that a downwardly facing shoulder of a bottom opening of the alignment plate is seated on a setback of the stiffener frame, wherein the bottom opening of the alignment plate is larger than the a top opening of the alignment plate. The circuit board is positioned on the stiffener frame. The alignment plate restrains movement of the circuit board relative to the stiffener frame with a peripheral wall of a the top opening of the alignment plate.

Abstract translation: 公开了用于将加强框架耦合到电路板的方法和装置。 一方面，提供了一种用于接合加强框架和定位在固定装置中的电路板的方法。 该方法包括将对准板定位在加强框架上，使得对准板的底部开口的向下的肩部位于加强框架的挫折上，其中对准板的底部开口大于顶部 对准板的开口。 电路板位于加强框架上。 对准板限制了电路板相对于加强框架的移动，同时具有对准板的顶部开口的周壁。

公开(公告)号：US20160143139A1

公开(公告)日：2016-05-19

申请号：US14938091

申请日：2015-11-11

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Haruo Sorimachi ,  Tetsuya Koyama

IPC: H05K1/11 ,  H05K1/09 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/181 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/00 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/141 ,  H05K3/4694 ,  H05K2201/0367 ,  H05K2201/1053 ,  H05K2201/10674 ,  Y02P70/611

Abstract: An electronic component device includes a first insulating layer, a wiring layer, a second insulating layer, a wiring component, and first and second electronic components. The first insulating layer includes a mounting region on an upper surface thereof. The wiring layer is formed on the first insulating layer except the mounting region. The second insulating layer is formed on the first insulating layer, is formed with an opening in the mounting region, and is formed with first and second connection holes on the wiring layer. The wiring component is mounted in the mounting region and in the opening and includes first and second connecting portions. The first electronic component is connected to the first connecting portion and is connected to the wiring layer in the first connection hole. The second electronic component is connected to the second connecting portion and is connected to the wiring layer in second connection hole.

Abstract translation: 电子部件装置包括第一绝缘层，布线层，第二绝缘层，布线部件以及第一和第二电子部件。 第一绝缘层包括在其上表面上的安装区域。 布线层形成在除了安装区域之外的第一绝缘层上。 第二绝缘层形成在第一绝缘层上，在安装区域形成有开口，并且在布线层上形成有第一和第二连接孔。 布线部件安装在安装区域和开口中，并且包括第一和第二连接部分。 第一电子部件连接到第一连接部分并连接到第一连接孔中的布线层。 第二电子部件连接到第二连接部，并且在第二连接孔中连接到布线层。