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    Transistor structure with silicided source and drain extensions and process for fabrication
    62.
    发明授权
    Transistor structure with silicided source and drain extensions and process for fabrication 有权
    具有硅化源和漏极延伸的晶体管结构以及制造工艺

    公开(公告)号：US08877595B2

    公开(公告)日：2014-11-04

    申请号：US13287409

    申请日：2011-11-02

    Applicant: Manoj Mehrotra

    Inventor： Manoj Mehrotra

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/285

    CPC classification number: H01L29/456 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/78 ,  H01L29/7845

    Abstract: A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch.

    Abstract translation: 晶体管形成在沟道区域上具有栅极的半导体衬底中，与沟道区相邻的衬底中的源极/漏极延伸区域以及与源极/漏极延伸区域相邻的衬底中的源极/漏极区域。 在源极/漏极延伸区域和源极/漏极区域上形成硅化物，使得硅化物在源极/漏极延伸区域上具有第一厚度，并且在源极/漏极区域上具有第二厚度，其中第二厚度大于第一厚度 厚度。 源极/漏极延伸区上的硅化物降低晶体管串联电阻，从而提高晶体管性能，并且还可以在接触蚀刻期间保护源极/漏极延伸区域免受硅损耗和硅损坏。

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    63.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140322881A1

    公开(公告)日：2014-10-30

    申请号：US14326760

    申请日：2014-07-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

    IPC: H01L29/66

    CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

    Abstract translation: 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

    STRESS MEMORIZATION IN RMG FINFETS
    67.
    发明申请
    STRESS MEMORIZATION IN RMG FINFETS 有权
    应力记忆在RMG FINFETS

    公开(公告)号：US20140239415A1

    公开(公告)日：2014-08-28

    申请号：US13778314

    申请日：2013-02-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Veeraraghavan S. Basker ,  Qing Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

    IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

    CPC classification number: H01L21/8238 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/785

    Abstract: Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate dielectric; depositing a stressor over the channel region of the transistor structure, wherein the stressor provides a stress to the channel region; removing the stressor metal after the stress is memorized within the channel region; and depositing a work function metal over the channel region of the transistor structure, where the work function metal applies less stress to the channel region than the stress applied by the stressor. A transistor with memorized stress includes a source and drain region on a substrate; a stress-memorized channel region on the substrate that retains an externally applied stress; and a gate structure including a work function gate metal that applies less stress to the stress-memorized channel region than the externally applied stress.

    Abstract translation: 具有记忆应力的晶体管和制造这种晶体管的方法。 所述方法包括形成具有沟道区，源极和漏极区以及栅极电介质的晶体管结构; 在所述晶体管结构的沟道区上沉积应力器，其中所述应力源向所述沟道区提供应力; 在应力存储在通道区域内之前去除应力金属; 以及在所述晶体管结构的沟道区域上沉积功函数金属，其中所述功函数金属对所述沟道区施加比由所述应力源施加的应力更小的应力。 具有记忆应力的晶体管包括衬底上的源区和漏区; 衬底上的应力记忆通道区域，其保持外部施加的应力; 以及包括与外部施加的应力相比对应力存储的沟道区域施加较小应力的功函栅极金属的栅极结构。

    Low noise and high performance LSI device
    68.
    发明授权
    Low noise and high performance LSI device 有权
    低噪声，高性能的LSI器件

    公开(公告)号：US08816440B2

    公开(公告)日：2014-08-26

    申请号：US12984261

    申请日：2011-01-04

    Applicant: Shigenobu Maeda ,  Jeong Hwan Yang

    Inventor： Shigenobu Maeda ,  Jeong Hwan Yang

    IPC: H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC classification number: H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

    Abstract translation: 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

    Inducing channel strain via encapsulated silicide formation
    70.
    发明授权
    Inducing channel strain via encapsulated silicide formation 有权
    通过封装的硅化物形成诱导通道应变

    公开(公告)号：US08796099B2

    公开(公告)日：2014-08-05

    申请号：US13705242

    申请日：2012-12-05

    Applicant: International Business Machines Corporation

    Inventor： Emre Alptekin ,  Ahmet S. Ozcan ,  Viraj Y. Sardesai ,  Cung D. Tran

    IPC: H01L21/336

    CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76889 ,  H01L23/485 ,  H01L29/66575 ,  H01L29/7845

    Abstract: Methods of forming semiconductor structures having channel regions strained by encapsulated silicide formation. Embodiments include forming a transistor, depositing an interlevel dielectric (ILD) layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal-rich silicide layers on the exposed portions of the source/drain regions, forming metal contacts in the contact recesses above the metal-rich silicide layers, and converting the metal-rich silicide layer to a silicon-rich silicide layer. In other embodiments, the metal-rich silicide layers are formed on the source/drain regions prior to ILD layer deposition. Embodiments further include forming a transistor, depositing an ILD layer above the transistor, forming contact recesses exposing portions of source/drain regions of the transistor, forming metal liners in the contact recesses, forming metal fills in the contact recesses, and forming silicide layers on the source/drain regions by reacting portions of the metal liners with portions of the source/drain regions.

    Abstract translation: 形成具有通过封装的硅化物形成应变的沟道区的半导体结构的方法。 实施例包括形成晶体管，在晶体管上方沉积层间电介质（ILD）层，形成露出晶体管的源极/漏极区的部分的接触凹部，在源/漏区的暴露部分上形成富金属硅化物层，形成 在富金属硅化物层上方的接触凹部中的金属接触，并将富金属硅化物层转化为富含硅的硅化物层。 在其它实施例中，在ILD层沉积之前，在源/漏区上形成富金属硅化物层。 实施例还包括形成晶体管，在晶体管上沉积ILD层，形成暴露晶体管的源/漏区部分的接触凹槽，在接触凹槽中形成金属衬垫，在接触凹槽中形成金属填充物，并在 源极/漏极区域通过使金属衬垫的部分与源/漏区的部分反应。

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