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    Methods of forming nano-scale pores, nano-scale electrical contacts, and memory devices including nano-scale electrical contacts, and related structures and devices
    1.
    发明授权
    Methods of forming nano-scale pores, nano-scale electrical contacts, and memory devices including nano-scale electrical contacts, and related structures and devices 有权
    形成纳米尺度孔隙，纳米尺度电接点以及包括纳米尺度电接点的存储器件以及相关结构和器件的方法

    公开(公告)号：US08877628B2

    公开(公告)日：2014-11-04

    申请号：US13547228

    申请日：2012-07-12

    申请人： Jun Liu ,  Kunal R. Parekh

    发明人： Jun Liu ,  Kunal R. Parekh

    IPC分类号： H01L21/44

    CPC分类号： H01L45/16 ,  H01L21/0337 ,  H01L21/76807 ,  H01L21/76816 ,  H01L27/2472 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

    摘要翻译： 电触点可以通过沿电介质结构的侧壁形成电介质衬垫而形成电介质衬垫，沿着牺牲结构的侧壁在电介质衬垫之上形成牺牲衬垫，并且在电介质衬垫的横向方向上形成牺牲衬垫，在电介质衬垫和牺牲衬套的交点处选择性地去除介质衬垫的部分， 形成孔，并且用导电材料至少部分地填充孔。 可以通过类似的方法形成纳米尺度的孔。 可以形成底部电极，并且电触点可以在结构上和电耦合到底部电极以形成存储器件。 纳米级电触点可以具有第一宽度和第二宽度的矩形横截面，每个宽度小于约20nm。 存储器件可以包括底部电极，具有小于约150nm 2的横截面积并且电耦合到底部电极的电触点，以及电触点上的电池材料。

    Semiconductor constructions and electronic systems
    3.
    发明授权
    Semiconductor constructions and electronic systems 有权
    半导体结构和电子系统

    公开(公告)号：US08344436B2

    公开(公告)日：2013-01-01

    申请号：US13196761

    申请日：2011-08-02

    申请人： Kunal R. Parekh

    发明人： Kunal R. Parekh

    IPC分类号： H01L27/108

    CPC分类号： H01L29/78 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1207 ,  H01L29/0603 ,  H01L29/7841

    摘要： Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

    摘要翻译： 一些实施例包括具有在SOI上部分延伸的晶体管栅极的DRAM以及形成这种DRAM的方法。 DRAM的单位单元可以在有源区域基座内，并且在一些实施例中，单位单元可以包括具有与有源区域基座的侧壁直接接触的存储节点的电容器。 一些实施例包括具有完全在SOI上的晶体管栅极的OC1T存储器，以及形成这种0C1T存储器的方法。

    Methods of forming recessed access devices associated with semiconductor constructions
    5.
    发明授权
    Methods of forming recessed access devices associated with semiconductor constructions 有权
    形成与半导体结构相关联的凹陷接入设备的方法

    公开(公告)号：US08067286B2

    公开(公告)日：2011-11-29

    申请号：US13012675

    申请日：2011-01-24

    申请人： Kunal R. Parekh ,  Suraj J. Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

    发明人： Kunal R. Parekh ,  Suraj J. Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L27/10823

    摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

    摘要翻译： 本发明包括形成凹入进入装置的方法。 提供基板以在其中具有凹入的接入装置沟槽。 一对凹进的接入设备沟槽彼此相邻。 导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。 导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。 在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

    Semiconductor Constructions And Electronic Systems
    6.
    发明申请
    Semiconductor Constructions And Electronic Systems 有权
    半导体建筑与电子系统

    公开(公告)号：US20110284940A1

    公开(公告)日：2011-11-24

    申请号：US13196761

    申请日：2011-08-02

    申请人： Kunal R. Parekh

    发明人： Kunal R. Parekh

    IPC分类号： H01L27/108

    CPC分类号： H01L29/78 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1207 ,  H01L29/0603 ,  H01L29/7841

    摘要： Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

    摘要翻译： 一些实施例包括具有在SOI上部分延伸的晶体管栅极的DRAM以及形成这种DRAM的方法。 DRAM的单位单元可以在有源区域基座内，并且在一些实施例中，单位单元可以包括具有与有源区域基座的侧壁直接接触的存储节点的电容器。 一些实施例包括具有完全在SOI上的晶体管栅极的OC1T存储器，以及形成这种0C1T存储器的方法。

    Methods of Forming Field Effect Transistors, Methods of Forming Field Effect Transistor Gates, Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array and Circuitry Peripheral to the Gate Array, and Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array Including First Gates and Second Grounded Isolation Gates
    8.
    发明申请
    Methods of Forming Field Effect Transistors, Methods of Forming Field Effect Transistor Gates, Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array and Circuitry Peripheral to the Gate Array, and Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array Including First Gates and Second Grounded Isolation Gates 有权
    形成场效应晶体管的方法，形成场效应晶体管门的方法，形成包括晶体管栅极阵列的集成电路的方法和栅极阵列的电路周边以及包括第一栅极和第二栅极的晶体管栅极阵列的集成电路的形成方法 隔离门

    公开(公告)号：US20110124168A1

    公开(公告)日：2011-05-26

    申请号：US13017508

    申请日：2011-01-31

    申请人： Young Pil Kim ,  Kunal R. Parekh

    发明人： Young Pil Kim ,  Kunal R. Parekh

    IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/4763

    CPC分类号： H01L21/823462 ,  H01L21/823456 ,  H01L21/823487 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621

    摘要： The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括形成场效应晶体管的方法，形成场效应晶体管栅极的方法，形成集成电路的方法，该集成电路包括晶体管栅极阵列和外围于栅极阵列的电路，以及形成集成电路的方法，该集成电路包括晶体管栅极阵列，其包括第一栅极 和第二接地隔离门。 在一个实施方案中，形成场效应晶体管的方法包括在衬底的半导体材料上形成掩模材料。 通过掩模材料形成沟槽并进入半导体材料。 栅介电材料形成在半导体材料的沟槽内。 栅极材料沉积在掩模材料中的沟槽内并且在半导体材料中的沟槽内沉积在栅极电介质材料上。 形成源/漏区。 考虑了其他方面和实现。

    Wafer processing including forming trench rows and columns at least one of which has a different width
    9.
    发明授权
    Wafer processing including forming trench rows and columns at least one of which has a different width 有权
    晶片处理包括形成沟槽行和列，其中至少一个具有不同的宽度

    公开(公告)号：US07897485B2

    公开(公告)日：2011-03-01

    申请号：US12504385

    申请日：2009-07-16

    申请人： Kunal R. Parekh

    发明人： Kunal R. Parekh

    IPC分类号： H01L21/46 ,  H01L21/78 ,  H01L21/301

    CPC分类号： H01L21/78

    摘要： Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a number of trenches of a particular depth in rows and columns. The method further includes forming a passivation layer on side walls of the number of trenches. The method also includes cutting a second side of the semiconductor wafer in rows and columns aligned with the number of trenches such that the semiconductor wafer singulates into a number of dice.

    摘要翻译： 本文描述了处理半导体晶片的方法。 一个实施例包括去除半导体晶片的第一侧的部分以在行和列中形成特定深度的多个沟槽。 该方法还包括在多个沟槽的侧壁上形成钝化层。 该方法还包括以与沟槽数对准的行和列切割半导体晶片的第二侧，使得半导体晶片被切割成多个管芯。