公开(公告)号：US09252188B2

公开(公告)日：2016-02-02

申请号：US13298840

申请日：2011-11-17

申请人： Sanh D. Tang ,  Scott E. Sills ,  John K. Zahurak

发明人： Sanh D. Tang ,  Scott E. Sills ,  John K. Zahurak

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/085 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

摘要： Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.

摘要翻译： 一些实施例包括形成存储器单元的方法。 形成一系列轨道以包括底部电极接触材料。 牺牲材料被图案化成跨越一系列轨道的一系列线。 一系列线的图案被转移到底部电极接触材料中。 牺牲材料的至少一部分随后被顶部电极材料代替。 一些实施例包括包含与第一系列导电线交叉的第二系列导电线的存储器阵列。 存储单元位于第二系列的导电线与第一系列的导电线重叠的位置处。 第一和第二存储单元材料位于存储单元位置内。 第一存储单元材料被配置为平面片，并且第二存储单元材料被配置为向上开口的容器。

公开(公告)号：US08772848B2

公开(公告)日：2014-07-08

申请号：US13191293

申请日：2011-07-26

申请人： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

发明人： John K. Zahurak ,  Sanh D. Tang ,  Lars P. Heineck ,  Martin C. Roberts ,  Wolfgang Mueller ,  Haitao Liu

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2454 ,  H01L29/36 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices. The conductive straps include the conductive material and individually are electrically coupled to a plurality of the vertical circuit devices in the array region. Other implementations are disclosed.

摘要翻译： 电路结构包括具有阵列区域和周边区域的基板。 阵列和外围区域中的衬底包括在第一半导体材料上的绝缘体材料，绝缘体材料上方的导电材料和导电材料上的第二半导体材料。 阵列区域包括包括第二半导体材料的垂直电路器件。 外围区域包括包括第二半导体材料的水平电路器件。 外围区域中的水平电路器件分别具有包括第二半导体材料的浮体。 外围区域中的导电材料在浮体的第二半导体材料的下面并电耦合。 阵列区域中的导电带在垂直电路装置下方。 导电带包括导电材料，并且单独地电耦合到阵列区域中的多个垂直电路器件。 公开了其他实现。

公开(公告)号：US08723252B2

公开(公告)日：2014-05-13

申请号：US13605511

申请日：2012-09-06

申请人： Gurtej Sandhu ,  John K. Zahurak ,  Jay Parks

发明人： Gurtej Sandhu ,  John K. Zahurak ,  Jay Parks

IPC分类号： H01L29/66

CPC分类号： H01L27/2454 ,  H01L27/2463 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

摘要翻译： 从半导体基底直立的垂直半导体材料，其在第一和第二掺杂区域之间形成导电通道。 第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层。 第二掺杂区域电耦合到台面的上表面上的多个第二硅化物层中的一个。 栅极导体设置在台面的一个或多个侧壁上。

公开(公告)号：US08643110B2

公开(公告)日：2014-02-04

申请号：US13446806

申请日：2012-04-13

申请人： Fernando Gonzalez ,  John K. Zahurak

发明人： Fernando Gonzalez ,  John K. Zahurak

IPC分类号： H01L29/786 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/0214 ,  H01L27/10858 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

摘要翻译： 绝缘体上硅器件具有形成在SOI的绝缘体层中的局部偏置结构。 局部偏置结构包括图案化导体，其向SOI的硅层的不同区域提供偏置信号。 导体凹陷到绝缘体层中以提供与硅层基本平坦的界面。 导体连接到偏置电压源。 在一个实施例中，提供分别连接到多个电压源的多个导体。 因此，硅层的不同区域被不同的偏置信号偏置。

公开(公告)号：US08546864B2

公开(公告)日：2013-10-01

申请号：US12825211

申请日：2010-06-28

申请人： Sanh D. Tang ,  John K. Zahurak

发明人： Sanh D. Tang ,  John K. Zahurak

IPC分类号： H01L29/76 ,  G11C11/34 ,  G11C16/04

摘要： Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

公开(公告)号：US20130011977A1

公开(公告)日：2013-01-10

申请号：US13609997

申请日：2012-09-11

申请人： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

发明人： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

IPC分类号： H01L21/336

CPC分类号： H01L27/10802 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/7841

摘要： Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

公开(公告)号：US20120300530A1

公开(公告)日：2012-11-29

申请号：US13117889

申请日：2011-05-27

申请人： Roy E. Meade ,  John K. Zahurak

发明人： Roy E. Meade ,  John K. Zahurak

IPC分类号： G11C11/21

CPC分类号： G11C7/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069

摘要： Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

摘要翻译： 描述与存储器单元操作相关联的方法，设备和系统。 操作存储器单元的一种或多种方法包括将耦合到存储器单元的电容器充电到特定的电压电平，并通过控制存储器的电阻式开关元件的电容放电来将存储器单元从第一状态编程到第二状态 细胞。

公开(公告)号：US08253191B2

公开(公告)日：2012-08-28

申请号：US13291591

申请日：2011-11-08

申请人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

发明人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

IPC分类号： H01L29/66

CPC分类号： H01L29/7827 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

摘要翻译： 从半导体基底直立的垂直半导体材料，其在第一和第二掺杂区域之间形成导电通道。 第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层。 第二掺杂区域电耦合到台面的上表面上的第二硅化物层。 栅极导体设置在台面的一个或多个侧壁上。

公开(公告)号：US08148225B2

公开(公告)日：2012-04-03

申请号：US12401555

申请日：2009-03-10

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US20120049272A1

公开(公告)日：2012-03-01

申请号：US13291591

申请日：2011-11-08

申请人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

发明人： Gurtej Sandhu ,  Chandra Mouli ,  John K. Zahurak

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

摘要翻译： 从半导体基底直立的垂直半导体材料，其在第一和第二掺杂区域之间形成导电通道。 第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层。 第二掺杂区域电耦合到台面的上表面上的第二硅化物层。 栅极导体设置在台面的一个或多个侧壁上。