公开(公告)号：US09575727B2

公开(公告)日：2017-02-21

申请号：US14497777

申请日：2014-09-26

申请人： Karthik Sarpatwari ,  Hongmei Wang ,  Sanjay Rangan

发明人： Karthik Sarpatwari ,  Hongmei Wang ,  Sanjay Rangan

IPC分类号： G06F7/58 ,  G09C1/00 ,  G11C13/00 ,  H04L9/08 ,  H04L9/32

CPC分类号： G06F21/44 ,  G06F7/58 ,  G06F7/588 ,  G09C1/00 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

摘要： Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.

摘要翻译： 公开和描述了可操作以产生随机数的装置和系统。 这样包括电耦合到被配置为初始地将阵列中的所有单元设置为高状态的电路的相变材料单元的阵列，通过阵列发送编程脉冲，该阵列具有足以将每个单元随机地设置为高状态或 低状态以在阵列上产生单元状态的随机分布，并且读取阵列外的单元状态的随机分布。

公开(公告)号：US08273619B2

公开(公告)日：2012-09-25

申请号：US12848662

申请日：2010-08-02

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US20100297822A1

公开(公告)日：2010-11-25

申请号：US12848662

申请日：2010-08-02

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US07767514B2

公开(公告)日：2010-08-03

申请号：US11406863

申请日：2006-04-18

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US07674670B2

公开(公告)日：2010-03-09

申请号：US11406893

申请日：2006-04-18

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US07224020B2

公开(公告)日：2007-05-29

申请号：US11287038

申请日：2005-11-23

申请人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

发明人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

IPC分类号： H01L29/788

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/41758 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7854 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： An integrated circuit device having non-linear active area pillars. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The pillars are patterned to form non-linear active area lines having angled segments. The conductive layer is patterned to form word lines that intersect the active area lines at the angled segments.

摘要翻译： 具有非线性有源区域支柱的集成电路装置。 更具体地，在衬底中形成支柱，使得侧壁被暴露。 支柱的侧壁和柱的顶表面被栅极氧化物和导电层覆盖以形成通过柱的通道。 支柱被图案化以形成具有成角度段的非线性有源面积线。 导电层被图案化以形成与成角度段的有源区域线相交的字线。

公开(公告)号：US20050035408A1

公开(公告)日：2005-02-17

申请号：US10931507

申请日：2004-09-01

申请人： Hongmei Wang ,  Zhongze Wang

发明人： Hongmei Wang ,  Zhongze Wang

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/94 ,  H01L21/338 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L47/00

CPC分类号： H01L29/66628 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66636

摘要： The invention provides a technique to fabricate a dielectric plug in a MOSFET. The dielectric plug is fabricated by forming an oxide layer over exposed source and drain regions in the substrate including a gate electrode stack. The formed oxide layer in the source and drain regions are then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode stack to form the dielectric plug and a channel region between the source and drain regions.

摘要翻译： 本发明提供了一种制造MOSFET中的电介质塞的技术。 通过在包括栅极电极堆叠的衬底中的暴露的源极和漏极区域上形成氧化物层来制造电介质插塞。 然后基本上除去源极和漏极区域中形成的氧化物层以暴露源极和漏极区域中的衬底并且将氧化物层的一部分留在栅极电极堆叠下方以形成电介质插塞以及在源极之间的沟道区域 和漏区。

公开(公告)号：US20130049096A1

公开(公告)日：2013-02-28

申请号：US13222602

申请日：2011-08-31

申请人： Hongmei Wang

发明人： Hongmei Wang

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/16 ,  H01L29/7889 ,  H01L29/7926

摘要： Various embodiments include methods and apparatuses including strings of memory cells formed along levels of semiconductor material. One such apparatus includes a stack comprised of a number of levels of single crystal silicon and a number of levels of dielectric material. Each of the levels of silicon is separated from an adjacent level of silicon by a level of the dielectric material. Strings of memory cells are formed along the levels of silicon. Additional apparatuses and methods are disclosed.

公开(公告)号：US20090176338A1

公开(公告)日：2009-07-09

申请号：US12401555

申请日：2009-03-10

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L21/84

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US07440255B2

公开(公告)日：2008-10-21

申请号：US10624340

申请日：2003-07-21

申请人： Brent A. McClure ,  Casey R. Kurth ,  Shenlin Chen ,  Debra K. Gould ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Fred D. Fishburn ,  Hongmei Wang

发明人： Brent A. McClure ,  Casey R. Kurth ,  Shenlin Chen ,  Debra K. Gould ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Fred D. Fishburn ,  Hongmei Wang

IPC分类号： H01G4/005

CPC分类号： H01L28/84 ,  H01L27/0805 ,  H01L27/10867 ,  H01L27/10873 ,  H01L28/75 ,  H01L28/91

摘要： A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.

摘要翻译： 电容器结构包括第一电极和第一电极与支撑电容器结构的表面之间的层。 与其他相同的电容器结构相比，电容器结构可以表现出较低的RC时间常数。 或者或另外，第一电极可以包含Si，并且该层可以限制Si对第一电极和支撑表面之间的金属硅化物材料的形成有贡献。 该层可以是氮化物层，并且可以是导电的或绝缘的。 当导电时，该层可以表现出大于第一电极的第二电导率的第一电导率。 电容器结构可用于存储器件中。