公开(公告)号：US20180342482A1

公开(公告)日：2018-11-29

申请号：US16055294

申请日：2018-08-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Meng-Tse Chen ,  Hui-Min Huang ,  Chih-Fan Huang ,  Ming-Da Cheng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/58 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31 ,  H01L21/3105 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538 ,  H01L21/56 ,  H01L23/15

CPC classification number: H01L25/0655 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/78 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/564 ,  H01L23/585 ,  H01L24/02 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.

公开(公告)号：US20180342450A1

公开(公告)日：2018-11-29

申请号：US15977195

申请日：2018-05-11

Applicant: Corning Incorporated

Inventor： Tian Huang ,  Yuhui Jin ,  Matthew Evan Wilhelm

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/15 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16235

Abstract: Articles and semiconductor packages that incorporate glass-based substrates are disclosed, as well as methods of forming thereof An article includes a glass-based substrate comprising first and second major surfaces spaced a distance from and parallel to each other, and a tapered via extending through the substrate. The tapered via includes a cross section that is symmetrical about a plane that is between and equidistant to the first and second major surfaces of the glass-based substrate and an interior wall with a first tapered region and a second tapered region positioned between the first major surface and the plane. The respective slopes of the first and second tapered regions are constant and the slope of the first tapered region is not equal to the slope of the second tapered region.

公开(公告)号：US20180310402A1

公开(公告)日：2018-10-25

申请号：US15882063

申请日：2018-01-29

Applicant: KYOCERA Corporation

Inventor： Isamu KIRIKIHIRA

IPC: H05K1/03 ,  H01L23/15 ,  C04B35/14

CPC classification number: H05K1/0306 ,  C04B35/14 ,  C04B35/584 ,  C04B2235/3206 ,  C04B2235/3224 ,  C04B2235/85 ,  C04B2237/32 ,  H01L23/15 ,  H01L23/3731 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: There is provided a ceramic substrate including: a silicon nitride crystal phase containing a plurality of silicon nitride crystals, and grain boundaries between the silicon nitride crystals; and a silicate phase containing magnesium silicate crystals and rare earth silicate crystals, respective maximum particle sizes of the magnesium silicate crystals and the rare earth silicate crystals being smaller than that of the silicon nitride crystals, the silicate phase being positioned in the grain boundaries.

公开(公告)号：US10079212B2

公开(公告)日：2018-09-18

申请号：US15279444

申请日：2016-09-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Naoki Takizawa

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/492 ,  H01L23/498 ,  H01L23/15 ,  H01L23/31 ,  H01L23/00 ,  H01L23/482 ,  H01L23/373 ,  H01L25/18 ,  H01L29/16 ,  H01L29/739 ,  H01L29/861 ,  H02M7/5387 ,  H01L23/13 ,  H02M7/00

CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3735 ,  H01L23/48 ,  H01L23/4824 ,  H01L23/492 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/18 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/7393 ,  H01L29/861 ,  H01L2224/32225 ,  H02M7/003 ,  H02M7/5387

Abstract: In order to restrict cracking or the like in a connection member such as solder, provided is a semiconductor device including a first component; a second component that is arranged on a front surface of the first component; and a connection portion that is provided between the first component and the second component and connects the second component to the first component. A first groove and a second groove having different shapes are formed in the front surface of the first component at positions opposite a first corner and a second corner of the second component, and the connection portion is also formed within the first groove and the second groove.

公开(公告)号：US20180254239A1

公开(公告)日：2018-09-06

申请号：US15446109

申请日：2017-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vijay SUKUMARAN ,  Ivan Junju HUANG ,  Saket CHADDA ,  Elavarasan T. PANNERSELVAM ,  Chok W. HO

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/15

Abstract: Methods for reliable interconnect structures between thin metal capture pads and TGV metallization and resulting devices are provided. Embodiments include forming a TGV in a glass substrate; filling with metal conductive paste; forming a metal layer on top and bottom surfaces of the substrate; patterning the metal layer, leaving at least a portion over the TGV top surface and an area surrounding the TGV; forming a dielectric layer on the metal layer and on the substrate top and bottom surfaces; patterning the dielectric layer, including exposing the metal layer over the TGV top surface and the area surrounding the TGV; forming a second metal layer on the dielectric layer and on the exposed portion of the first metal layer over the TGV top surface and the area surrounding the TGV; patterning the second metal layer exposing the dielectric layer; and forming a third metal layer on the second metal layer.

公开(公告)号：US10070533B2

公开(公告)日：2018-09-04

申请号：US15276363

申请日：2016-09-26

Applicant: 3D GLASS SOLUTIONS, INC

Inventor： Jeb H. Flemming ,  Jeff Bullington ,  Roger Cook ,  Kyle McWethy

IPC: H05K1/11 ,  H05K1/16 ,  H05K3/10 ,  H05K3/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H05K1/03

CPC classification number: H05K3/107 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/5286 ,  H05K1/0306 ,  H05K3/0023 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003

Abstract: The present invention includes compositions and methods of creating electrical isolation and ground plane structures, around electronic devices (inductors, antenna, resistors, capacitors, transmission lines and transformers) in photo definable glass ceramic substrates in order to prevent parasitic electronic signals, RF signals, differential voltage build up and floating grounds from disrupting and degrading the performance of isolated electronic devices by the fabrication of electrical isolation and ground plane structures on a photo-definable glass substrate.

公开(公告)号：US20180219090A1

公开(公告)日：2018-08-02

申请号：US15747423

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Kimin JUN ,  Il-Seok SON ,  Donald W. NELSON

IPC: H01L29/78 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L29/78 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/05 ,  H01L29/41791 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/16227

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US10014237B2

公开(公告)日：2018-07-03

申请号：US15535122

申请日：2015-12-14

Applicant: KYOCERA Corporation

Inventor： Shinichi Kooriyama ,  Narutoshi Ogawa ,  Masashi Konagai ,  Kensou Ochiai ,  Noritaka Niino

IPC: H01L23/15 ,  H01L33/64 ,  H01L51/52 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3735 ,  H01L21/4857 ,  H01L23/12 ,  H01L23/13 ,  H01L23/15 ,  H01L23/373 ,  H01L23/3736 ,  H01L33/641 ,  H01L51/529 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/0002 ,  H05K1/02 ,  H01L2924/00014

Abstract: A circuit board includes an insulating substrate; a metal circuit sheet joined to a first principal surface of the insulating substrate; and a heat dissipating sheet made of metal and joined to a second principal surface of the insulating substrate, the second principal surface being opposite the first principal surface. The thickness of the heat dissipating sheet is at least 3.75 times the thickness of the metal circuit sheet. The size of metal grains contained in the heat dissipating sheet is smaller than the size of metal grains contained in the metal circuit sheet, and decreases with increasing distance from the second principal surface of the insulating substrate.

公开(公告)号：US10008458B2

公开(公告)日：2018-06-26

申请号：US15316217

申请日：2015-06-16

Applicant: SONY CORPORATION

Inventor： Kosuke Hareyama

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/49 ,  H01L25/18 ,  H01P3/08 ,  H01P11/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/081 ,  H01P11/003 ,  H01L2924/00

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device capable of realizing impedance control of the semiconductor device.An input/output wiring line 23 and a ground wiring line 22 are such that through glass vias are provided so as to form a strip line structure by blasting or electric discharge machining and thereafter metal films are formed on a surface and a rear surface. It is possible to configure the semiconductor device with the impedance control by adjusting a conductor diameter of the input/output wiring line 23 and an insulating layer thickness between the input/output wiring line 23 and the ground wiring line 22. The present technology may be applied to the semiconductor device.

公开(公告)号：US20180166353A1

公开(公告)日：2018-06-14

申请号：US15753889

申请日：2016-08-19

Applicant: Corning Incorporated

Inventor： Sean Matthew Garner ,  Jen-Chieh Lin ,  Michael Lesley Sorensen

IPC: H01L23/15 ,  C03B33/02 ,  C03C17/00 ,  C03C23/00 ,  H01L21/48 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K3/0029 ,  C03B33/0222 ,  C03C15/00 ,  C03C17/002 ,  C03C17/008 ,  C03C23/0025 ,  C03C23/007 ,  C03C2217/445 ,  C03C2217/70 ,  H01L21/4807 ,  H01L23/15 ,  H05K1/024 ,  H05K1/028 ,  H05K1/0306 ,  H05K1/036 ,  H05K1/115 ,  H05K3/002 ,  H05K3/107 ,  H05K3/388 ,  H05K3/4038 ,  H05K3/4629 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2203/0143 ,  H05K2203/0743 ,  H05K2203/075 ,  H05K2203/0776 ,  H05K2203/0789 ,  H05K2203/107 ,  H05K2203/1194 ,  H05K2203/1545 ,  Y02P40/57

Abstract: Glass substrate assemblies having low dielectric properties, electronic assemblies incorporating glass substrate assemblies, and methods of fabricating glass substrate assemblies are disclosed. In one embodiment, a substrate assembly includes a glass layer 110 having a first surface and a second surface, and a thickness of less than about 300 μm. The substrate assembly further includes a dielectric layer 120 disposed on at least one of the first surface or the second surface of the glass layer. The dielectric layer has a dielectric constant value of less than about 3.0 in response to electromagnetic radiation having a frequency of 10 GHz. In some embodiments, the glass layer is made of annealed glass such that the glass layer has a dielectric constant value of less than about 5.0 and a dissipation factor value of less than about 0.003 in response to electromagnetic radiation having a frequency of 10 GHz. An electrically conductive layer 142 is disposed on a surface of the dielectric layer, within the dielectric layer or under the dielectric layer.