公开(公告)号：US08791549B2

公开(公告)日：2014-07-29

申请号：US12832019

申请日：2010-07-07

申请人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

发明人： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/81 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/811 ,  H01L2224/8136 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

摘要翻译： 集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。 金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。 金属线包括双镶嵌结构。 集成电路结构还包括覆盖金属线的凸块。

公开(公告)号：US20140203438A1

公开(公告)日：2014-07-24

申请号：US13745366

申请日：2013-01-18

申请人： TAIWAN SEMICONDUCTOR MAUFACTURING COMPANY, LTD.

发明人： Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Jie Chen ,  Ying-Ju Chen

IPC分类号： H01L21/02 ,  H01L23/538

CPC分类号： H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/05 ,  H01L24/08 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13007 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

摘要： Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad.

摘要翻译： 公开了在电介质层上形成凸块下金属化（UBM）焊盘的方法和装置。 电介质层可以在金属层之上，并且包括围绕第一开口的第一开口和第二开口，其将电介质层分成第一区域和第二区域。 UBM垫延伸并填充介电层的第一开口，位于第一开口和第二开口之间的第一区域上方，并且还可以进一步向下延伸至第二开口，第二开口覆盖第二开口的一部分或全部 的介电层。 如果UBM垫填充介电层的整个第二开口，则UBM垫可以进一步延伸到电介质层的第二区域的一部分上。 焊球可以安装在UBM垫上。

公开(公告)号：US08788738B2

公开(公告)日：2014-07-22

申请号：US13311392

申请日：2011-12-05

申请人： Yoshiro Riho

发明人： Yoshiro Riho

IPC分类号： G06F3/06 ,  G06F13/00

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C7/20 ,  G11C8/12 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  H01L23/481 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05087 ,  H01L2224/05096 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13564 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/00 ,  H01L2224/05552

摘要： Disclosed herein is a device that includes a first terminal operatively supplied with a pulse signal, a second terminal, a set of third terminals operatively supplied with identification information, a storage unit configured to store the identification information in response to the pulse signal, and a control unit configured to electrically disconnect the first terminal from the second terminal until the storage unit stores the identification information and electrically connect the first terminal to the second terminal after the storage unit has stored the identification information. This device may be used as each of semiconductor chips that are stacked with each other.

摘要翻译： 本文公开了一种装置，其包括可操作地提供有脉冲信号的第一端子，第二端子，可操作地提供有识别信息的一组第三端子，被配置为响应于脉冲信号存储识别信息的存储单元，以及 所述控制单元被配置为从所述第二终端电气断开所述第一终端，直到所述存储单元存储所述识别信息，并且在所述存储单元存储所述识别信息之后将所述第一终端电连接到所述第二终端。 该装置可以用作彼此堆叠的每个半导体芯片。

公开(公告)号：US20140167259A1

公开(公告)日：2014-06-19

申请号：US14186869

申请日：2014-02-21

申请人： Micron Technology, Inc.

发明人： Owen R. Fay ,  Luke G. England ,  Christopher J. Gambee

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L21/0274 ,  H01L21/311 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/35121 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2224/11

摘要： Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polyimide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

摘要翻译： 制造用于半导体晶片的互连结构的方法包括形成与导电元件的全柱直径上的有源表面上的接合焊盘接触的导电元件，随后将包含光致抗蚀剂的可光限定材料施加到有源表面上并在导电元件上 。 聚酰亚胺材料被选择性地曝光和显影以除去覆盖至少导电元件顶部的可光限定材料。 还公开了半导体管芯和半导体管芯组件。

公开(公告)号：US20140110837A1

公开(公告)日：2014-04-24

申请号：US14132739

申请日：2013-12-18

申请人： Roden Topacio ,  Gabriel Wong

发明人： Roden Topacio ,  Gabriel Wong

IPC分类号： H01L23/498

CPC分类号： H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05599 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

摘要： A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

摘要翻译： 公开了一种用于半导体管芯的布线层。 布线层包括用于附接焊料凸块的焊盘; 键合焊盘键合到具有集成电路的管芯的凸点焊盘，并且将焊接接合焊盘贴到焊盘上。 布线层形成在介电材料层上。 路由层包括至少部分地围绕一些焊盘的导电迹线，以便吸收附着到焊盘的焊料凸起的应力。 围绕焊盘的迹线的一部分保护靠近焊料凸块的基底电介质材料的部分免受应力的影响。

公开(公告)号：US08629557B2

公开(公告)日：2014-01-14

申请号：US13414877

申请日：2012-03-08

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/48 ,  H01L21/00 ,  B23K31/00

CPC分类号： H01L22/30 ,  H01L22/12 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05584 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13028 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2924/01029

摘要： Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

摘要翻译： 用于检测基座侧壁焊料润湿的结构和方法。 该结构包括具有集成电路芯片阵列的半导体晶片，每个集成电路芯片具有芯片基座阵列，其具有位于芯片基座顶部的相应的芯片焊料柱，基座沿第一方向隔开第一距离;以及 在垂直于第一方向的第二方向上间隔开的第二距离; 以及设置在所述晶片与所述集成电路芯片的不同区域中的至少一个监视器结构，所述监视器结构至少包括在所述第一基座的顶表面上的第一基座和第一焊料柱，以及第二基座和第二焊接柱 在第二基座的顶表面上，第一和第二基座间隔第三距离，第三距离小于第一和第二距离。

公开(公告)号：US20140008798A1

公开(公告)日：2014-01-09

申请号：US14006614

申请日：2011-03-22

申请人： Shinji Baba ,  Masaki Watanabe ,  Muneharu Tokunaga ,  Kazuyuki Nakagawa

发明人： Shinji Baba ,  Masaki Watanabe ,  Muneharu Tokunaga ,  Kazuyuki Nakagawa

IPC分类号： H01L23/498

CPC分类号： H01L24/17 ,  H01L21/563 ,  H01L23/291 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/1134 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.

摘要翻译： 提供了能够提高半导体器件的可靠性的技术。 在本发明中，作为安装有半导体芯片的布线基板，不使用积层布线板，而是使用贯通布线板THWB。 以这种方式，在本发明中，仅使用芯层形成的贯通布线板，因此不需要考虑堆积层与芯层之间的热膨胀系数的差异， 不需要考虑由于积聚层不存在而在积层中形成的精细通孔的电断开。 结果，根据本发明，可以提高半导体器件的可靠性，同时降低成本。

公开(公告)号：US08618678B2

公开(公告)日：2013-12-31

申请号：US12265439

申请日：2008-11-05

申请人： Chiu-Shun Lin

发明人： Chiu-Shun Lin

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/1412 ,  H01L2224/16245 ,  H01L2224/81125 ,  H01L2924/00013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

摘要： A chip structure and a chip package structure are disclosed herein. The chip structure includes a chip and a bump. The chip includes at least one pad. The bump is disposed on a bounding region of the pad. The shape of the bump is triangular pillar or trapezoidal pillar. A surface area of connection between the bump and the pad is less than or equal to the bounding region. Therefore, the material usage and the cost of the bump can be reduced. In addition, such shape of the bump has directional characteristic so that it is easy to perform the chip testing via the identifiable pads, and perform the package process of bonding the chip to a circuit board or any carriers.

摘要翻译： 本文公开了一种芯片结构和芯片封装结构。 芯片结构包括芯片和凸块。 该芯片包括至少一个焊盘。 凸块设置在垫的边界区域上。 凸块的形状是三角柱或梯形柱。 凸起和垫之间的连接表面积小于或等于边界区域。 因此，可以减少材料的使用和冲击的成本。 此外，凸起的这种形状具有方向特性，使得容易通过可识别的焊盘执行芯片测试，并且执行将芯片接合到电路板或任何载体的封装处理。

公开(公告)号：US08507317B2

公开(公告)日：2013-08-13

申请号：US13093032

申请日：2011-04-25

申请人： Mark A. Bachman ,  Donald S. Bitting ,  Sailesh Chittipeddi ,  Seung H. Kang ,  Sailesh M. Merchant

发明人： Mark A. Bachman ,  Donald S. Bitting ,  Sailesh Chittipeddi ,  Seung H. Kang ,  Sailesh M. Merchant

IPC分类号： H01L21/60

CPC分类号： H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552

摘要： The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

摘要翻译： 本发明在一个方面提供一种半导体器件，其包括位于半导体衬底之上的互连层。 钝化层位于互连层上并且具有形成在其中的焊料凸块支撑开口。 包括导电材料的支撑柱位于焊料凸块支撑开口内。

公开(公告)号：US08501614B1

公开(公告)日：2013-08-06

申请号：US13426810

申请日：2012-03-22

申请人： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Hua-An Dai

发明人： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Cheng-Fan Lin ,  Hua-An Dai

IPC分类号： H01L21/44

CPC分类号： H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/05666 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2224/05552

摘要： A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion.

摘要翻译： 制造细间距凸块的方法包括以下步骤：提供硅衬底; 在所述硅衬底上形成含钛金属层，其中所述含钛金属层包括多个第一区和多个第二区; 在含钛金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口槽; 在开口槽处形成多个铜凸块，其中每个铜凸块包括第一顶表面和环表面; 加热光致抗蚀剂层以形成多个主体部分和多个可移除部分; 蚀刻光致抗蚀剂层; 以及移除所述第二区域以使得所述第一区域中的每一个能够形成具有轴承部分和延伸部分的凸起下金属层。