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    SEMICONDUCTOR DEVICE AND METHOD INCLUDING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD INCLUDING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE 有权
    半导体器件和方法，包括提供更换缺陷位线的冗余位线

    公开(公告)号：US20140140155A1

    公开(公告)日：2014-05-22

    申请号：US14163368

    申请日：2014-01-24

    申请人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

    发明人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

    IPC分类号： G11C29/00

    CPC分类号： G11C29/785 ,  G11C11/406 ,  G11C29/783 ,  G11C29/808 ,  G11C29/83

    摘要： A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.

    摘要翻译： 一种方法包括：基于行地址选择包括在多个存储器阵列之一中的字线，其中多个存储器阵列中的每一个包括多个字线，多个位线和冗余位线，选择 基于列地址包括在所选择的存储器存储器中的位线之一，响应于列地址，由列浮动电路选择冗余位线来代替要选择的位线中的一个位置 所述列地址指示缺陷地址，当响应于第一命令提供所述行地址时激活所述列浮动电路，以及当响应于第二命令提供所述行地址时，使所述列浮动电路失活。

    SEMICONDUCTOR DEVICE HAVING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE
    3.
    发明申请
    SEMICONDUCTOR DEVICE HAVING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE 失效
    具有冗余位线的半导体器件提供更换有缺陷的位线

    公开(公告)号：US20120213021A1

    公开(公告)日：2012-08-23

    申请号：US13396985

    申请日：2012-02-15

    申请人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

    发明人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

    IPC分类号： G11C29/04

    CPC分类号： G11C29/785 ,  G11C11/406 ,  G11C29/783 ,  G11C29/808 ,  G11C29/83

    摘要： Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.

    摘要翻译： 本文公开了一种响应于垫选择信息的装置，其用于选择存储器垫之一，并且从例如存储在熔丝电路中的多个缺陷地址中选择至少一个缺陷地址。 当访问地址信息与选择的缺陷地址一致时，访问冗余存储单元来代替正常存储单元读取或写入数据。 另一方面，在刷新操作中，包括上述用冗余存储单元替换正常存储单元的列寻址被去激活。

    Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address
    4.
    发明授权
    Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address 有权
    半导体存储器件及其控制方法以及用于确定缺陷地址修复可能性的方法

    公开(公告)号：US07940583B2

    公开(公告)日：2011-05-10

    申请号：US12320892

    申请日：2009-02-06

    申请人： Yoshiro Riho ,  Jun Suzuki ,  Yasuhiro Matsumoto ,  Shuichi Kubouchi ,  Hiromasa Noda ,  Yasuji Koshikawa

    发明人： Yoshiro Riho ,  Jun Suzuki ,  Yasuhiro Matsumoto ,  Shuichi Kubouchi ,  Hiromasa Noda ,  Yasuji Koshikawa

    IPC分类号： G11C29/00

    CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C29/84

    摘要： There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.

    摘要翻译： 提供有多个存储器垫，子字驱动器，其访问正常存储器单元，而不管请求访问的行地址是否是缺陷地址;子字驱动器，访问属于 当行地址是缺陷地址时，由行地址指示的正常存储单元不同的存储器垫。 根据本发明，正常存储单元和冗余存储单元属于彼此不同的存储器单元，从而可以在确定修复确定电路的操作的同时访问正常存储单元。

    DEVICE
    5.
    发明申请
    DEVICE 审中-公开
    设备

    公开(公告)号：US20110085366A1

    公开(公告)日：2011-04-14

    申请号：US12889976

    申请日：2010-09-24

    申请人： Yoshiro Riho

    发明人： Yoshiro Riho

    IPC分类号： G11C5/02

    CPC分类号： G11C5/04 ,  G11C7/1072 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A device includes first to N-th (N is an integer of 2 or more) semiconductor chips stacked. These semiconductor chips have substantially the same configuration, and each includes an identification flag memory circuit including first to N-th memory units and a plurality of through electrodes connected to the identification flag memory circuit. Each of the through electrodes is connected to or masked with respect to the corresponding one of the through electrodes of the underlying semiconductor chip, such that an identification flag is stored in n-th (n indicates 1, 2, . . . , and N) memory units of the n-th semiconductor chips sequentially in the stacking order in response to a clock signal input in common to the first to N-th semiconductor chips, and the storage of the identification flag in the N-th memory unit of the N-th semiconductor chip can be detected from the lower side of the first semiconductor chip.

    摘要翻译： 一种器件包括第一至第N（N为2以上的整数）半导体芯片堆叠。 这些半导体芯片具有基本相同的结构，并且每个包括识别标志存储电路，该标识存储电路包括第一至第N存储器单元和连接到识别标志存储电路的多个通孔。 每个贯通电极相对于下面的半导体芯片的贯通电极中相应的一个电极连接或掩蔽，使得识别标志被存储在第n（n表示1,2，...，N ）第n个半导体芯片的存储器单元，其响应于与第一至第N个半导体芯片共同输入的时钟信号，以堆叠顺序顺序地进行，并且识别标志在第N个半导体芯片的第N个存储器单元中的存储 可以从第一半导体芯片的下侧检测第N个半导体芯片。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07864618B2

    公开(公告)日：2011-01-04

    申请号：US12137802

    申请日：2008-06-12

    申请人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

    发明人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

    IPC分类号： G11C8/00

    CPC分类号： G11C5/025 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48

    摘要： A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.

    摘要翻译： 半导体存储器件包括多个存储体，每个存储体由在纵向方向上串联排列的多个存储单元阵列构成，其中每个存储单元阵列包括多个存储单元，并且其中存储单元阵列 银行被集体地聚集成多个块，每个块包括与多个DQ焊盘相关联的在垂直方向上排列的存储单元阵列。 DQ垫布置在块附近。 在存储单元和DQ垫之间基本上设置相同的距离，以便相对于所有DQ焊盘减少访问时间的分散，从而实现半导体存储器件中的高速访问。 在芯片的中心区域，IO线的布线区域减小。

    Semiconductor memory device having sense amplifier
    7.
    发明申请
    Semiconductor memory device having sense amplifier 审中-公开
    具有读出放大器的半导体存储器件

    公开(公告)号：US20100103758A1

    公开(公告)日：2010-04-29

    申请号：US12588730

    申请日：2009-10-26

    申请人： Yoshiro Riho ,  Shuichi Kubouchi

    发明人： Yoshiro Riho ,  Shuichi Kubouchi

    IPC分类号： G11C7/02 ,  G11C5/14

    CPC分类号： G11C7/08 ,  G11C5/147 ,  G11C11/4091 ,  H01L27/10897

    摘要： To provide a first power supply wiring that supplies a lower-side write potential to a sense amplifier, a second power supply wiring that supplies a higher-side write potential to the sense amplifier, a third power supply wiring that supplies an overdrive potential to the sense amplifier, and a stabilizing capacitance arranged between the first power supply wiring and the third power supply wiring. With this configuration, a capacitance value applied to the lower-side write potential and a capacitance value applied to the overdrive potential inevitably match, and thus fluctuation of the lower-side write potential and fluctuation of the overdrive potential at an initial stage of a sense operation are offset.

    摘要翻译： 为了提供向读出放大器提供下侧写入电位的第一电源布线，向读出放大器提供较高侧写入电位的第二电源布线，向第一电源布线提供过驱动电位的第三电源布线 读出放大器和布置在第一电源布线和第三电源布线之间的稳定电容。 利用这种结构，施加到下侧写入电位的电容值和施加于过驱动电位的电容值不可避免地匹配，从而在感觉的初始阶段下侧写入电位的波动和过驱动电位的波动 操作被偏移。

    SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND REFRESH CONTROL METHOD
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND REFRESH CONTROL METHOD 审中-公开
    半导体存储器件，半导体器件，存储器系统和刷新控制方法

    公开(公告)号：US20080212386A1

    公开(公告)日：2008-09-04

    申请号：US11964303

    申请日：2007-12-26

    申请人： Yoshiro RIHO

    发明人： Yoshiro RIHO

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/406 ,  G11C5/025 ,  G11C8/06 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/40622

    摘要： A semiconductor memory device comprises: a memory cell array in which memory cells are divided into banks; cache memories each for storing data of a word line selected by a row address; a setting register for setting a data holding capacity so that a holding area where data is held during a self refresh period and a non-holding area where data is not held during the self refresh period are commonly included in each bank; a refresh controller for outputting a row address to be refreshed at predetermined intervals during the self refresh period and for performing a refresh operation for a selected word line corresponding to the row address in an activated bank; and a bank controller for activating all banks when the selected word line is included in the holding area and inactivating all banks when the selected word Line is included in the non-holding area.

    摘要翻译： 半导体存储器件包括：存储器单元阵列，其中存储器单元被划分为存储体; 高速缓存存储器，用于存储由行地址选择的字线的数据; 一个设置寄存器，用于设置数据保持容量，使得在自刷新周期期间保持数据的保持区域和在自刷新周期期间不保持数据的非保持区域通常包括在每个存储体中; 刷新控制器，用于在自刷新周期期间以预定间隔输出要刷新的行地址，并且用于对与激活的存储体中的行地址相对应的所选字线执行刷新操作; 以及当所选择的字线被包括在保持区域中时激活所有存储体的存储体控制器，并且当所选择的字线被包括在非保持区域中时使所有存储体停用。

    REFERENCE VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    9.
    发明申请
    REFERENCE VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    参考电压发生电路和半导体集成电路器件

    公开(公告)号：US20080211572A1

    公开(公告)日：2008-09-04

    申请号：US12018375

    申请日：2008-01-23

    申请人： Yoshiro RIHO

    发明人： Yoshiro RIHO

    IPC分类号： G05F3/16

    CPC分类号： G11C11/4074 ,  G11C5/147 ,  G11C7/04 ,  G11C11/4099

    摘要： A reference voltage generating circuit comprises: a monitor circuit, including a low threshold voltage PMOS transistor, a low threshold voltage NMOS transistor, and a resistor having a predetermined resistance which are connected in series, for generating a reference voltage at one end; and an additional circuit for supplying a monitor current to the monitor circuit and for controlling the other end of the monitor circuit to be at a constant voltage, wherein a voltage value of the reference voltage is corrected within a range corresponding to a process fluctuation from a predetermined center value, based on the monitor current changing in response to the process fluctuation.

    摘要翻译： 参考电压产生电路包括：监测电路，包括低阈值电压PMOS晶体管，低阈值电压NMOS晶体管和串联连接的具有预定电阻的电阻器，用于在一端产生参考电压; 以及附加电路，用于向监视电路提供监视电流，并将监视器电路的另一端控制在恒定电压，其中参考电压的电压值在对应于来自 基于监视电流响应于过程波动而改变的预定中心值。