公开(公告)号：US08638625B2

公开(公告)日：2014-01-28

申请号：US13396985

申请日：2012-02-15

申请人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

发明人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

IPC分类号： G11C7/00

CPC分类号： G11C29/785 ,  G11C11/406 ,  G11C29/783 ,  G11C29/808 ,  G11C29/83

摘要： Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.

摘要翻译： 本文公开了一种响应于垫选择信息的装置，其用于选择存储器垫之一，并且从例如存储在熔丝电路中的多个缺陷地址中选择至少一个缺陷地址。 当访问地址信息与选择的缺陷地址一致时，访问冗余存储单元来代替正常存储单元读取或写入数据。 另一方面，在刷新操作中，包括上述用冗余存储单元替换正常存储单元的列寻址被去激活。

公开(公告)号：US08837242B2

公开(公告)日：2014-09-16

申请号：US14163368

申请日：2014-01-24

申请人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

发明人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

IPC分类号： G11C7/00

CPC分类号： G11C29/785 ,  G11C11/406 ,  G11C29/783 ,  G11C29/808 ,  G11C29/83

摘要： A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.

摘要翻译： 一种方法包括：基于行地址选择包括在多个存储器阵列之一中的字线，其中多个存储器阵列中的每一个包括多个字线，多个位线和冗余位线，选择 基于列地址包括在所选择的存储器存储器中的位线之一，响应于列地址，由列浮动电路选择冗余位线来代替要选择的位线中的一个位置 所述列地址指示缺陷地址，当响应于第一命令提供所述行地址时激活所述列浮动电路，以及当响应于第二命令提供所述行地址时，使所述列浮动电路失活。

公开(公告)号：US20140140155A1

公开(公告)日：2014-05-22

申请号：US14163368

申请日：2014-01-24

申请人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

发明人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

IPC分类号： G11C29/00

CPC分类号： G11C29/785 ,  G11C11/406 ,  G11C29/783 ,  G11C29/808 ,  G11C29/83

摘要： A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.

摘要翻译： 一种方法包括：基于行地址选择包括在多个存储器阵列之一中的字线，其中多个存储器阵列中的每一个包括多个字线，多个位线和冗余位线，选择 基于列地址包括在所选择的存储器存储器中的位线之一，响应于列地址，由列浮动电路选择冗余位线来代替要选择的位线中的一个位置 所述列地址指示缺陷地址，当响应于第一命令提供所述行地址时激活所述列浮动电路，以及当响应于第二命令提供所述行地址时，使所述列浮动电路失活。

公开(公告)号：US20120213021A1

公开(公告)日：2012-08-23

申请号：US13396985

申请日：2012-02-15

申请人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

发明人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

IPC分类号： G11C29/04

CPC分类号： G11C29/785 ,  G11C11/406 ,  G11C29/783 ,  G11C29/808 ,  G11C29/83

摘要： Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.

摘要翻译： 本文公开了一种响应于垫选择信息的装置，其用于选择存储器垫之一，并且从例如存储在熔丝电路中的多个缺陷地址中选择至少一个缺陷地址。 当访问地址信息与选择的缺陷地址一致时，访问冗余存储单元来代替正常存储单元读取或写入数据。 另一方面，在刷新操作中，包括上述用冗余存储单元替换正常存储单元的列寻址被去激活。

公开(公告)号：US08004325B2

公开(公告)日：2011-08-23

申请号：US12469265

申请日：2009-05-20

申请人： Yoshio Mizukane ,  Hiroki Fujisawa

发明人： Yoshio Mizukane ,  Hiroki Fujisawa

IPC分类号： H03L7/06

CPC分类号： H03L7/06 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/10

摘要： A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.

摘要翻译： 时钟发生电路连接到用于控制DLL电路等的操作定时的计数器电路的设备，并且通过从时钟产生电路向计数器电路间歇地提供时钟信号来间歇地操作计数器电路。

公开(公告)号：US08270228B2

公开(公告)日：2012-09-18

申请号：US12797948

申请日：2010-06-10

申请人： Yoshio Mizukane ,  Hiroki Fujisawa

发明人： Yoshio Mizukane ,  Hiroki Fujisawa

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1066 ,  G11C7/20 ,  G11C11/4072 ,  G11C17/14 ,  G11C17/143 ,  G11C17/18

摘要： A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.

摘要翻译： 半导体器件包括熔丝元件，读出电路，其响应于响应于外部复位信号的转变被激活的第一内部复位信号而读取熔丝元件的存储器内容;以及锁存电路，其保持 其中由读出电路读出的存储器内容，并通过基于外部复位信号的激活周期被激活的第二内部复位信号复位。 由此，即使在外部复位信号的激活期间长的情况下，也能够缩短电流流过保险丝元件的时间，从而能够减少复位动作时的电流消耗。

公开(公告)号：US20100302875A1

公开(公告)日：2010-12-02

申请号：US12797948

申请日：2010-06-10

申请人： Yoshio Mizukane ,  Hiroki Fujisawa

发明人： Yoshio Mizukane ,  Hiroki Fujisawa

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1066 ,  G11C7/20 ,  G11C11/4072 ,  G11C17/14 ,  G11C17/143 ,  G11C17/18

摘要： A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.

摘要翻译： 半导体器件包括熔丝元件，读出电路，其响应于响应于外部复位信号的转变被激活的第一内部复位信号而读取熔丝元件的存储器内容;以及锁存电路，其保持 其中由读出电路读出的存储器内容，并通过基于外部复位信号的激活周期被激活的第二内部复位信号复位。 由此，即使在外部复位信号的激活期间长的情况下，也能够缩短电流流过保险丝元件的时间，从而能够减少复位动作时的电流消耗。

公开(公告)号：US20090289677A1

公开(公告)日：2009-11-26

申请号：US12469265

申请日：2009-05-20

申请人： Yoshio Mizukane ,  Hiroki Fujisawa

发明人： Yoshio Mizukane ,  Hiroki Fujisawa

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H03L7/06 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/10

摘要： A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.

摘要翻译： 时钟发生电路连接到用于控制DLL电路等的操作定时的计数器电路的设备，并且通过从时钟发生电路向计数器电路间歇地提供时钟信号来间歇地操作计数器电路。

公开(公告)号：US08493110B2

公开(公告)日：2013-07-23

申请号：US13184273

申请日：2011-07-15

申请人： Yoshio Mizukane ,  Hiroki Fujisawa

发明人： Yoshio Mizukane ,  Hiroki Fujisawa

IPC分类号： H03L7/06

CPC分类号： H03L7/06 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/0812 ,  H03L7/10

摘要： A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.

公开(公告)号：US20100208528A1

公开(公告)日：2010-08-19

申请号：US12695784

申请日：2010-01-28

申请人： Yoshio Mizukane ,  Hiroki Fujisawa

发明人： Yoshio Mizukane ,  Hiroki Fujisawa

IPC分类号： G11C7/10 ,  G11C17/16 ,  G11C7/00

CPC分类号： G11C11/4072 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/20

摘要： A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.