公开(公告)号：US08717795B2

公开(公告)日：2014-05-06

申请号：US13565666

申请日：2012-08-02

申请人： Hayato Oishi ,  Hisayuki Nagamine

发明人： Hayato Oishi ,  Hisayuki Nagamine

IPC分类号： G11C5/02

CPC分类号： G11C8/12 ,  G11C5/063 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/005

摘要： Disclosed herein is a device that includes first and second ports arranged in a first direction and first and second circuits arranged between the first and second ports. The first and second ports are coupled to the first and second circuits, respectively. The first and second circuits include first and second sub circuits that control an operation timing thereof based on a timing signal, respectively. The control signal is transmitted through a control line extending in a second direction. Distances between the control line and the first and second sub circuits in the first direction are the same as each other. A coordinate of the control line in the first direction is different from an intermediate coordinate between coordinates of the first and second ports in the first direction.

摘要翻译： 这里公开了一种装置，其包括沿第一方向布置的第一和第二端口以及布置在第一和第二端口之间的第一和第二电路。 第一和第二端口分别耦合到第一和第二电路。 第一和第二电路包括分别基于定时信号控制其操作定时的第一和第二子电路。 控制信号通过沿第二方向延伸的控制线传输。 控制线与第一和第二子电路在第一方向上的距离彼此相同。 控制线在第一方向上的坐标与第一方向上的第一和第二端口的坐标之间的中间坐标不同。

公开(公告)号：US20130033916A1

公开(公告)日：2013-02-07

申请号：US13565666

申请日：2012-08-02

申请人： Hayato OISHI ,  Hisayuki NAGAMINE

发明人： Hayato OISHI ,  Hisayuki NAGAMINE

IPC分类号： G11C5/06

CPC分类号： G11C8/12 ,  G11C5/063 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/005

摘要： Disclosed herein is a device that includes first and second ports arranged in a first direction and first and second circuits arranged between the first and second ports. The first and second ports are coupled to the first and second circuits, respectively. The first and second circuits include first and second sub circuits that control an operation timing thereof based on a timing signal, respectively. The control signal is transmitted through a control line extending in a second direction. Distances between the control line and the first and second sub circuits in the first direction are the same as each other. A coordinate of the control line in the first direction is different from an intermediate coordinate between coordinates of the first and second ports in the first direction.

摘要翻译： 这里公开了一种装置，其包括沿第一方向布置的第一和第二端口以及布置在第一和第二端口之间的第一和第二电路。 第一和第二端口分别耦合到第一和第二电路。 第一和第二电路包括分别基于定时信号控制其操作定时的第一和第二子电路。 控制信号通过沿第二方向延伸的控制线传输。 控制线与第一和第二子电路在第一方向上的距离彼此相同。 控制线在第一方向上的坐标与第一方向上的第一和第二端口的坐标之间的中间坐标不同。

公开(公告)号：US07864618B2

公开(公告)日：2011-01-04

申请号：US12137802

申请日：2008-06-12

申请人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

发明人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

IPC分类号： G11C8/00

CPC分类号： G11C5/025 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48

摘要： A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.

摘要翻译： 半导体存储器件包括多个存储体，每个存储体由在纵向方向上串联排列的多个存储单元阵列构成，其中每个存储单元阵列包括多个存储单元，并且其中存储单元阵列 银行被集体地聚集成多个块，每个块包括与多个DQ焊盘相关联的在垂直方向上排列的存储单元阵列。 DQ垫布置在块附近。 在存储单元和DQ垫之间基本上设置相同的距离，以便相对于所有DQ焊盘减少访问时间的分散，从而实现半导体存储器件中的高速访问。 在芯片的中心区域，IO线的布线区域减小。

公开(公告)号：US20090003026A1

公开(公告)日：2009-01-01

申请号：US12137802

申请日：2008-06-12

申请人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

发明人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

IPC分类号： G11C5/02 ,  G11C8/00

CPC分类号： G11C5/025 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48

摘要： A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.

摘要翻译： 半导体存储器件包括多个存储体，每个存储体由在纵向方向上串联排列的多个存储单元阵列构成，其中每个存储单元阵列包括多个存储单元，并且其中存储单元阵列 银行被集体地聚集成多个块，每个块包括与多个DQ焊盘相关联的在垂直方向上排列的存储单元阵列。 DQ垫布置在块附近。 在存储单元和DQ垫之间基本上设置相同的距离，以便相对于所有DQ焊盘减少访问时间的分散，从而实现半导体存储器件中的高速访问。 在芯片的中心区域，IO线的布线区域减小。

公开(公告)号：US07796453B2

公开(公告)日：2010-09-14

申请号：US12145240

申请日：2008-06-24

申请人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

发明人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

IPC分类号： G11C11/00

CPC分类号： G11C7/1048 ,  G11C7/1051 ,  G11C7/1069

摘要： A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.

摘要翻译： 半导体器件包括：列解码器，根据输入的列地址，生成列选择信号，该列选择信号选择存储单元连接到的多个位线对; 通过列选择信号连接多个位线对的位线选择开关和将从存储单元读出的数据输出到外部的数据I / O线对; 数据放大器，其放大数据I / O线对的电压差，并将已读取的数据输出到输出缓冲器; 在数据I / O线路中提供的数据I / O线路开关; 对不在数据放大器一侧的数据I / O线对进行预充电的I / O线路预充电电路; 以及对数据放大器侧面的数据I / O线对进行预充电的放大器预充电电路。

公开(公告)号：US20090003107A1

公开(公告)日：2009-01-01

申请号：US12145240

申请日：2008-06-24

申请人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

发明人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

IPC分类号： G11C7/12

CPC分类号： G11C7/1048 ,  G11C7/1051 ,  G11C7/1069

摘要： A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.

摘要翻译： 半导体器件包括：列解码器，根据输入的列地址，生成列选择信号，该列选择信号选择存储单元连接到的多个位线对; 通过列选择信号连接多个位线对的位线选择开关和将从存储单元读出的数据输出到外部的数据I / O线对; 数据放大器，其放大数据I / O线对的电压差，并将已读取的数据输出到输出缓冲器; 在数据I / O线路中提供的数据I / O线路开关; 对不在数据放大器一侧的数据I / O线对进行预充电的I / O线路预充电电路; 以及对数据放大器侧面的数据I / O线对进行预充电的放大器预充电电路。