公开(公告)号：US20120153492A1

公开(公告)日：2012-06-21

申请号：US12969836

申请日：2010-12-16

Applicant: Mark A. Bachman ,  Sailesh M. Merchant ,  John Osenbach

Inventor： Mark A. Bachman ,  Sailesh M. Merchant ,  John Osenbach

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are removed to thereby expose the fill material. At least portions of the exposed fill material are removed to form a back-side through-substrate via opening that traverses an entire thickness of the substrate. The back-side through-substrate via opening is filled with an electrically conductive material.

Abstract translation: 一种制造贯通基板通孔结构的方法。 该方法包括提供具有前侧和相对背面的基板。 在基板的前侧形成贯通基板通路孔。 贯通基板通孔开口不穿透基板背面的外表面。 贯通基板通孔开口填充有固体填充材料。 从衬底的背面的外表面去除衬底的部分，从而露出填充材料。 暴露的填充材料的至少部分被去除以形成穿过衬底的整个厚度的背面贯穿衬底通孔开口。 背面贯通基板通孔开口填充有导电材料。

公开(公告)号：US20120153430A1

公开(公告)日：2012-06-21

申请号：US12969852

申请日：2010-12-16

Applicant: Mark A. Bachman ,  Sailesh M. Merchant ,  John Osenbach

Inventor： Mark A. Bachman ,  Sailesh M. Merchant ,  John Osenbach

IPC: H01L23/52 ,  H01L21/76 ,  H01L21/44

CPC classification number: H01L21/76224 ,  H01L21/76837 ,  H01L21/76898 ,  H01L23/481 ,  H01L2221/1005 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Abstract translation: 一种制造IC的方法，包括提供具有第一侧和第二相对侧的衬底，在衬底的第一侧中形成STI开口，并在衬底的第一侧形成部分TSV开口，并延伸部分TSV 开放 扩展的部分TSV开口比STI开口更深入衬底。 该方法还包括用第一固体材料填充STI开口并用第二固体材料填充延伸的部分TSV开口。 STI打开，部分TSV打开，也不延伸部分TSV开口都不穿透基板的第二侧的外表面。 至少同时形成STI开口和部分TSV开口，或者同时填充STI开口和延伸部分TSV开口。

公开(公告)号：US07429502B2

公开(公告)日：2008-09-30

申请号：US11868624

申请日：2007-10-08

Applicant: Vance D. Archer, III ,  Kouros Azimi ,  Daniel Patrick Chesire ,  Warren K Gladden ,  Seung H. Kang ,  Taeho Kook ,  Sailesh M. Merchant ,  Vivian Ryan

Inventor： Vance D. Archer, III ,  Kouros Azimi ,  Daniel Patrick Chesire ,  Warren K Gladden ,  Seung H. Kang ,  Taeho Kook ,  Sailesh M. Merchant ,  Vivian Ryan

IPC: H01L21/00

CPC classification number: H01L23/36 ,  H01L21/4871 ,  H01L25/165 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract translation: 一种集成电路装置，其包括冶金结合以增强对散热器的热传导。 在半导体器件中，集成电路管芯的表面冶金地结合到散热器的表面。 在制造器件的示例性方法中，封装衬底的上表面包括内部区域和周边区域。 集成电路管芯位于衬底表面上，并且集成电路管芯的第一表面被放置成与封装衬底接触。 金属层形成在集成电路管芯的第二相对表面上。 预成型件定位在金属层上，并且散热器位于预制件上。 用预成型件形成接合层，将散热器冶金结合到集成电路管芯的第二表面。

公开(公告)号：US07005375B2

公开(公告)日：2006-02-28

申请号：US10260727

申请日：2002-09-30

Applicant: Subramanian Karthikeyan ,  Sailesh M. Merchant

Inventor： Subramanian Karthikeyan ,  Sailesh M. Merchant

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76814

Abstract: A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.

Abstract translation: 防止互连金属扩散到周围电介质材料中的方法。 在介电区域的开口中形成金属互连之前，清洁下面的金属表面，在该金属表面期间，金属可以沉积在开口的侧壁上。 这种金属可以扩散到电介质中并引起漏电流。 为了防止金属沉积到侧壁上，在金属表面清洁步骤之前，将阻挡层沉积到开口中并溅射到侧壁上。

公开(公告)号：US06699372B2

公开(公告)日：2004-03-02

申请号：US09836365

申请日：2001-04-16

Applicant: Siddhartha Bhowmik ,  Sailesh M. Merchant ,  Frank Minardi

Inventor： Siddhartha Bhowmik ,  Sailesh M. Merchant ,  Frank Minardi

IPC: C23C1434

CPC classification number: H01J37/321 ,  C23C14/32 ,  C23C14/3471 ,  C23C14/564

Abstract: The present invention provides a method of depositing a film on a surface of a coil that includes depositing a metal from a target onto a surface of a coil to form a first film on the surface and forming a second film over the first film at a low pressure and at a first power at the target that is substantially higher than a first power at the component's surface. The conditioned deposition tool is well suited for manufacturing integrated circuits.

Abstract translation: 本发明提供了一种在线圈表面上沉积薄膜的方法，该方法包括将金属从靶材沉积到线圈的表面上以在表面上形成第一薄膜，并在低温下在第一薄膜上形成第二薄膜 并且在目标处的第一功率基本上高于组件表面处的第一功率。 调理沉积工具非常适合制造集成电路。

公开(公告)号：US06403415B1

公开(公告)日：2002-06-11

申请号：US09481463

申请日：2000-01-11

Applicant: Glenn B. Alers ,  Sailesh M. Merchant ,  Pradip K. Roy

Inventor： Glenn B. Alers ,  Sailesh M. Merchant ,  Pradip K. Roy

IPC: H01L218242

CPC classification number: H01L28/56 ,  H01L21/31604 ,  H01L28/40 ,  H01L29/4966

Abstract: The present invention provides a semiconductor device that has a metal barrier layer for a dielectric material, which can be used in an integrated circuit, if so desired. The semiconductor device provides a capacitance to the integrated circuit and in a preferred embodiment comprises a first layer located on a surface of the integrated circuit. A metal barrier layer is located on the first layer and is susceptible to oxidation by oxygen. A high K capacitor dielectric layer (i.e., a higher K than silicon dioxide) that contains oxygen, such as tantalum pentoxide, is located over the metal barrier layer. The semiconductor device further includes a first layer located over the high K capacitor dielectric layer.

Abstract translation: 本发明提供一种半导体器件，其具有用于电介质材料的金属阻挡层，如果需要，其可用于集成电路中。 半导体器件为集成电路提供电容，并且在优选实施例中包括位于集成电路的表面上的第一层。 金属阻挡层位于第一层上，易氧化氧。 含有氧的高K电容电介质层（即比二氧化硅高的K），例如五氧化二钽，位于金属阻挡层的上方。 半导体器件还包括位于高K电容介电层上的第一层。

公开(公告)号：US06365511B1

公开(公告)日：2002-04-02

申请号：US09324946

申请日：1999-06-03

Applicant: Isik C. Kizilyalli ,  Sailesh M. Merchant ,  Joseph R. Radosevich

Inventor： Isik C. Kizilyalli ,  Sailesh M. Merchant ,  Joseph R. Radosevich

IPC: H01L214763

CPC classification number: H01L21/76838 ,  H01L21/76841

Abstract: The present invention provides a method of forming a metal stack structure over a substrate of a semiconductor device, comprising: (a) forming a first metal layer over the substrate, (b) forming a tungsten silicide nitride layer over the first metal layer, (c) forming a second metal layer over the tungsten silicide nitride layer, and (d) annealing the metal stack structure at a diffusion temperature. The tungsten silicide nitride layer inhibits diffusion of the metal in the metal stack. In one embodiment, the annealing is performed in the presence of a forming gas mixture comprising deuterium. In one particularly advantageous embodiment, the metal stack is formed in a contact opening or via. In yet other embodiments, the first metal layer may be a stack layer of titanium and titanium nitride and the second metal layer may be aluminum or copper.

Abstract translation: 本发明提供一种在半导体器件的衬底上形成金属堆叠结构的方法，包括：（a）在衬底上形成第一金属层，（b）在第一金属层上形成硅化钨化物层，（ c）在所述硅化钨氮化物层上形成第二金属层，和（d）在扩散温度下退火所述金属堆叠结构。 硅化钨层抑制金属堆叠中的金属的扩散。 在一个实施方案中，在包含氘的形成气体混合物的存在下进行退火。 在一个特别有利的实施例中，金属叠层形成在接触开口或通孔中。 在其它实施例中，第一金属层可以是钛和氮化钛的堆叠层，第二金属层可以是铝或铜。

公开(公告)号：US06359339B1

公开(公告)日：2002-03-19

申请号：US09480224

申请日：2000-01-10

Applicant: Richard W. Gregor ,  Isik C. Kizilyalli ,  Sailesh M. Merchant ,  Jaseph R. Radosevich ,  Pradip K. Roy

Inventor： Richard W. Gregor ,  Isik C. Kizilyalli ,  Sailesh M. Merchant ,  Jaseph R. Radosevich ,  Pradip K. Roy

IPC: H01L2348

CPC classification number: H01L28/24 ,  H01L27/0802

Abstract: The present invention provides a unique a resistor formed on a semiconductor substrate. The resistor preferably comprises a first resistor layer that includes a first metal silicide, such as tungsten silicide, and nitrogen and that is formed on the substrate. The first layer has a first thickness and a concentration of nitrogen incorporated therein. The nitrogen concentration may be varied to obtain a desired resistive value of the resistor. Thus, depending on the concentration of nitrogen, a wide range of resistive values may be achieved. The resistor further comprises a second resistor layer with a second thickness that includes a second metal silicide and that is formed on the first resistor layer. Thus, the present invention provides a metal silicide-based resistor having nitrogen incorporated therein which allows the resistance of the resistor to be tailored to specific electrical applications. Yet at the same time, the resistor is far less susceptible to temperature and voltage variation than conventional diffused resistors and, thereby, provides a more precise resistor.

Abstract translation: 本发明提供了形成在半导体衬底上的独特的电阻器。 电阻器优选地包括第一电阻层，该第一电阻层包括第一金属硅化物，例如硅化钨和氮，并且形成在衬底上。 第一层具有掺入其中的第一厚度和氮浓度。 可以改变氮浓度以获得电阻器的期望电阻值。 因此，取决于氮的浓度，可以实现宽范围的电阻值。 电阻器还包括具有第二厚度的第二电阻层，该第二电阻层包括第二金属硅化物，并形成在第一电阻层上。 因此，本发明提供一种其中结合有氮化物的金属硅化物基电阻器，其允许将电阻器的电阻定制为特定的电气应用。 然而与此同时，电阻器比常规扩散电阻器更不易受温度和电压变化的影响，从而提供更精确的电阻器。

公开(公告)号：US06355184B1

公开(公告)日：2002-03-12

申请号：US09427306

申请日：1999-10-26

Applicant: Annette M. Crevasse ,  William G. Easter ,  John A. Maze ,  Sailesh M. Merchant ,  Frank Miceli

Inventor： Annette M. Crevasse ,  William G. Easter ,  John A. Maze ,  Sailesh M. Merchant ,  Frank Miceli

IPC: H01L2100

CPC classification number: B24B57/02 ,  B24B1/04 ,  B24B37/04

Abstract: The present invention, in one embodiment, provides a method for eliminating agglomerate particles in a polishing slurry. In this particular embodiment, the method is directed to reducing agglomeration of slurry particles within a waste slurry passing through a slurry system drain. The method comprises conveying the waste slurry to the drain, wherein the waste slurry may form an agglomerate having an agglomerate particle size. The method further comprises subjecting the waste slurry to energy emanating from an energy source. The energy source thereby transfers energy to the waste slurry to substantially reduce the agglomerate particle size. Substantially reduce means that the agglomerate is size is reduced such that the waste slurry is free to flow through the drain.

公开(公告)号：US06281129B1

公开(公告)日：2001-08-28

申请号：US09399621

申请日：1999-09-20

Applicant: William G. Easter ,  John A. Maze ,  Sailesh M. Merchant

Inventor： William G. Easter ,  John A. Maze ,  Sailesh M. Merchant

IPC: H01L21302

CPC classification number: B24B53/017 ,  B24B53/12 ,  B24D3/06

Abstract: The present invention provides a method of manufacturing a semiconductor device using a polishing apparatus having a polishing pad conditioning wheel. In one embodiment, the polishing pad conditioning wheel comprises a conditioning head, a setting alloy, an abrasive material, and a corrosion resistant coating. The conditioning head has opposing first and second faces with the first face being coupleable to the polishing apparatus. The setting alloy is coupled to the conditioning head at the second face, and the abrasive material is embedded in the setting alloy, which is substantially covered by the corrosion resistant coating.

Abstract translation: 本发明提供使用具有抛光垫调节轮的抛光装置制造半导体器件的方法。 在一个实施例中，抛光垫调节轮包括调节头，定型合金，研磨材料和耐腐蚀涂层。 调节头具有相对的第一和第二面，其中第一面可与抛光装置相连。 该设定合金在第二面与该调节头相连，并且该研磨材料被嵌入该固化合金中，该合金基本被该耐腐蚀涂层覆盖。