公开(公告)号：US09067272B2

公开(公告)日：2015-06-30

申请号：US13659660

申请日：2012-10-24

Applicant: Arizona Board of Regents, a body corporate of the State of Arizona Acting for and on behalf of Arizona State University

Inventor： Jemmy Sutanto ,  Jitendran Muthuswamy

IPC: H05K7/00 ,  B23K1/20 ,  B05D5/10 ,  B23K1/00 ,  B23K1/008 ,  B23K3/06 ,  H01L23/00 ,  H01L25/065

CPC classification number: B23K1/20 ,  B23K1/0008 ,  B23K1/008 ,  B23K3/0607 ,  B23K3/0638 ,  B23K2101/42 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/14155 ,  H01L2224/16145 ,  H01L2224/48145 ,  H01L2225/06555 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15788 ,  H05K7/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: Interconnect and/or reflow methods of the present disclosure achieve high aspect ratio interconnects, for example interconnects having an aspect ratio as high as 4, in addition to wider interconnect height tolerances among interconnects (for example, interconnects having a height variability of up to about 30%) while still achieving reliable electrical connections. Moreover, flip-chip interconnects configured in accordance with principles of the present disclosure can provide improved z-axis spacing between die-to-die and/or die-to-substrate flip chip stacks, for example z-axis spacing as large as 600 μm. In this manner, additional spacing can be achieved for MEMS devices and/or similar components that are extendable and/or deformable out of the die plane.

Abstract translation: 本公开的互连和/或回流方法除了互连之间更宽的互连高度公差之外，还具有高纵横比互连，例如具有高达4的纵横比的互连（例如，具有高达约 30％），同时仍能实现可靠的电气连接。 此外，根据本公开的原理配置的倒装芯片互连可以提供管芯到管芯和/或管芯到衬底倒装芯片堆叠之间的改进的z轴间隔，例如大至600的z轴间距 μm。 以这种方式，可以为MEMS器件和/或可在模具平面外延伸和/或可变形的类似部件实现额外的间隔。

公开(公告)号：US09029196B2

公开(公告)日：2015-05-12

申请号：US12969467

申请日：2010-12-15

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L33/62

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11823 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯。 衬底具有互连部位的导电迹线。 导电凸块材料沉积在互连部位或模具凸块焊盘上。 将半导体管芯安装在衬底上，使得凸块材料设置在管芯凸块焊盘和互连部位之间。 凸块材料在管芯凸块焊盘或互连部位周围没有焊接掩模回流，以在管芯和衬底之间形成互连结构。 凸起材料在管芯凸块焊盘或互连部位内自我限制。 凸起材料的体积被选择为使得表面张力基本上保持凸块材料的自限制在模具凸块焊盘和互连部位的覆盖区内。 互连结构可以具有可熔部分和不可熔部分。 封装剂沉积在管芯和衬底之间。

公开(公告)号：US20150123270A1

公开(公告)日：2015-05-07

申请号：US14474686

申请日：2014-09-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi TSUKIYAMA ,  Masatoshi FUKUDA ,  Yukifumi OYAMA ,  Shinya FUKAYAMA

IPC: H01L23/00 ,  H01L25/07 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/074 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/10135 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/1415 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/1705 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/35 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/8185 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.

Abstract translation: 根据一个实施例，第一电极形成在第一半导体芯片的第一面上，第二电极和突起形成在第二半导体芯片的第二面上。 第一半导体芯片和第二半导体芯片通过突起彼此间隔开，使得第一面和第二面彼此面对。 第一半导体芯片和第二半导体芯片经受回流以彼此电连接，然后突起在低于回流温度的温度下固化。

公开(公告)号：US08884437B2

公开(公告)日：2014-11-11

申请号：US13686436

申请日：2012-11-27

Applicant: Infineon Technologies AG

Inventor： Klaus-Guenter Oppermann ,  Martin Franosch

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/488 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/488 ,  H01L21/486 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05599 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A device with contact elements. One embodiment provides an electrical device including a structure defining a main face. The structure includes an array of cavities and an array of overhang regions, each overhang region defining an opening to one of the cavities. The electrical device further includes an array of contact elements, each contact element only partially filling one of the cavities and protruding from the structure over the main face.

Abstract translation: 具有接触元件的设备。 一个实施例提供一种电气设备，其包括限定主面的结构。 该结构包括空腔阵列和突出区域阵列，每个悬出区域限定到一个空腔的开口。 电气装置还包括接触元件的阵列，每个接触元件仅部分地填充其中一个空腔并从主面上的结构突出。

公开(公告)号：US08759211B2

公开(公告)日：2014-06-24

申请号：US13793947

申请日：2013-03-11

Applicant: Napra Co., Ltd.

Inventor： Shigenobu Sekine ,  Yurina Sekine ,  Yoshiharu Kuwana ,  Ryuji Kimura

IPC: H01L21/4763

CPC classification number: H05K13/0465 ,  H01B3/025 ,  H01B3/10 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6616 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/1131 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/812 ,  H01L2224/8181 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01066 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/8384

Abstract: A method includes applying, between connection conductors of adjacent substrates, a junction material containing the first metal or alloy component and the second metal or alloy component having a higher melting point than said first metal or alloy component. The method further includes melting the junction material by a heat treatment.

Abstract translation: 一种方法包括在相邻基底的连接导体之间施加含有第一金属或合金成分的接合材料和具有比所述第一金属或合金成分更高的熔点的第二金属或合金成分。 该方法还包括通过热处理熔化接合材料。

公开(公告)号：US08541299B2

公开(公告)日：2013-09-24

申请号：US12787527

申请日：2010-05-26

Applicant: Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

Inventor： Stephen Leslie Buchwalter ,  Bruce K. Furman ,  Peter A. Gruber ,  Jae-Woong Nah ,  Da-Yuan Shih

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/28 ,  H01L24/31 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10242 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49165 ,  H01L2224/45111 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract translation: 电互连形成方法。 电互连包括包括第一导电焊盘的第一衬底，包括第二导电焊盘的第二衬底以及将第一导电焊盘电连接和机械地连接到第二导电焊盘的互连结构。 互连结构包括非焊料金属芯结构，第一焊料结构和第二焊料结构。 第一焊料结构将非焊料金属芯结构的第一部分电连接并机械地连接到第一导电焊盘。 第二焊料结构将非焊料金属芯结构的第二部分电连接并机械连接到第二导电焊盘。

公开(公告)号：US20130128484A1

公开(公告)日：2013-05-23

申请号：US13740698

申请日：2013-01-14

Applicant: Chaun Hu ,  Shawna M. Liff ,  Gregory S. Clemons

Inventor： Chaun Hu ,  Shawna M. Liff ,  Gregory S. Clemons

IPC: H05K1/18

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K1/181 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

公开(公告)号：US20130099385A1

公开(公告)日：2013-04-25

申请号：US13280157

申请日：2011-10-24

Applicant: Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Chun-Cheng Lin ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/538 ,  H01L21/66

CPC classification number: H01L25/50 ,  H01L21/31105 ,  H01L21/565 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/1131 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.

公开(公告)号：US20130070436A1

公开(公告)日：2013-03-21

申请号：US13659660

申请日：2012-10-24

Applicant: Arizona Board of Regents, a body corporate for

Inventor： Jemmy Sutanto ,  Jitendran Muthuswamy

IPC: H05K7/00 ,  B23K1/20 ,  B05D5/10

CPC classification number: B23K1/20 ,  B23K1/0008 ,  B23K1/008 ,  B23K3/0607 ,  B23K3/0638 ,  B23K2101/42 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/14155 ,  H01L2224/16145 ,  H01L2224/48145 ,  H01L2225/06555 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15788 ,  H05K7/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: Interconnect and/or reflow methods of the present disclosure achieve high aspect ratio interconnects, for example interconnects having an aspect ratio as high as 4, in addition to wider interconnect height tolerances among interconnects (for example, interconnects having a height variability of up to about 30%) while still achieving reliable electrical connections. Moreover, flip-chip interconnects configured in accordance with principles of the present disclosure can provide improved z-axis spacing between die-to-die and/or die-to-substrate flip chip stacks, for example z-axis spacing as large as 600 μm. In this manner, additional spacing can be achieved for MEMS devices and/or similar components that are extendable and/or deformable out of the die plane.

Abstract translation: 本公开的互连和/或回流方法除了互连之间更宽的互连高度公差之外，还具有高纵横比互连，例如具有高达4的纵横比的互连（例如，具有高达约 30％），同时仍能实现可靠的电气连接。 此外，根据本公开的原理配置的倒装芯片互连可以提供管芯到管芯和/或管芯到衬底倒装芯片堆叠之间的改进的z轴间隔，例如大至600的z轴间距 μm。 以这种方式，可以为MEMS器件和/或可在模具平面外延伸和/或可变形的类似部件实现额外的间隔。

公开(公告)号：US08371497B2

公开(公告)日：2013-02-12

申请号：US12482668

申请日：2009-06-11

Applicant: Christopher James Healy

Inventor： Christopher James Healy

IPC: B23K31/02 ,  B23K35/34 ,  B23K101/40

CPC classification number: H01L24/16 ,  H01L21/4867 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/1182 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/75 ,  H01L2224/7515 ,  H01L2224/7901 ,  H01L2224/81011 ,  H01L2224/8102 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/0401

Abstract: A flip chip packaging method to attach a die to a package substrate, the method including dipping the die into solder paste; placing the die onto the package substrate; and reflowing the solder paste to attach the die to the package substrate. Other embodiments are described and claimed.

Abstract translation: 一种用于将管芯附接到封装衬底的倒装芯片封装方法，所述方法包括将所述管芯浸入焊膏中; 将管芯放置在封装衬底上; 并回流焊膏以将管芯附接到封装衬底。 描述和要求保护其他实施例。