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    Semiconductor devices including SRAM cell and methods for fabricating the same
    52.
    发明授权
    Semiconductor devices including SRAM cell and methods for fabricating the same 有权
    包括SRAM单元的半导体器件及其制造方法

    公开(公告)号：US08860096B2

    公开(公告)日：2014-10-14

    申请号：US13009602

    申请日：2011-01-19

    Applicant: OhKyum Kwon ,  Byungsun Kim ,  Taejung Lee

    Inventor： OhKyum Kwon ,  Byungsun Kim ,  Taejung Lee

    IPC: H01L27/11 ,  H01L27/02

    CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/11 ,  Y10S257/909

    Abstract: An SRAM cell of a semiconductor device includes a load transistor, a driver transistor and an access transistor. First source/drains of the load, driver and access transistors are connected to a node. A power line, a ground line and a bit line are electrically connected to second source/drains of the load transistor, the driver transistor and the access transistor. The power line, the ground line and the bit line are disposed at substantially the same level to extend in a first direction. A word line is electrically connected to a gate of the access transistor to extend in a second direction perpendicular to the first direction. The word line is disposed at a different level from the level of the power line, the ground line and the bit line.

    Abstract translation: 半导体器件的SRAM单元包括负载晶体管，驱动晶体管和存取晶体管。 负载，驱动器和存取晶体管的第一源/漏极连接到节点。 电力线，地线和位线电连接到负载晶体管，驱动晶体管和存取晶体管的第二源极/漏极。 电力线，地线和位线被设置在基本上相同的水平面上，以沿第一方向延伸。 字线电连接到存取晶体管的栅极，以在垂直于第一方向的第二方向延伸。 字线设置在与电力线，地线和位线的电平不同的水平上。

    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning
    53.
    发明授权
    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning 有权
    用于三维矩阵阵列存储器布局的方法和装置，用于降低成本图案化

    公开(公告)号：US08809128B2

    公开(公告)日：2014-08-19

    申请号：US12911900

    申请日：2010-10-26

    Applicant: Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    IPC: H01L21/82 ,  H01L27/24

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.

    Abstract translation: 本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。 存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。 公开了许多附加方面。

    Semiconductor device including source strapping line
    56.
    发明申请
    Semiconductor device including source strapping line 失效
    半导体装置包括源带捆扎线

    公开(公告)号：US20070096187A1

    公开(公告)日：2007-05-03

    申请号：US11520817

    申请日：2006-09-14

    Applicant: Wook-Hyoung Lee

    Inventor： Wook-Hyoung Lee

    IPC: H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC classification number: H01L27/115 ,  H01L27/11521 ,  Y10S257/909

    Abstract: A semiconductor device includes a plurality of source regions and drain regions disposed on a semiconductor substrate. The semiconductor device also includes a plurality of word lines disposed on the semiconductor substrate between the source regions and the drain regions. The semiconductor device also includes a conductive line disposed on the semiconductor substrate parallel to the word lines. The semiconductor device also includes a plurality of bit lines connected to the drain regions and crossing over the word lines. The semiconductor device also includes a plurality of source strapping lines crossing over the plurality of word lines, the plurality of source strapping lines being connected to at least one of the plurality of source regions and the conductive line. The semiconductor device also includes a ground line connected to the conductive line.

    Abstract translation: 半导体器件包括设置在半导体衬底上的多个源极区和漏极区。 半导体器件还包括在源极区域和漏极区域之间设置在半导体衬底上的多个字线。 半导体器件还包括平行于字线设置在半导体衬底上的导线。 半导体器件还包括连接到漏区并跨越字线的多个位线。 半导体器件还包括跨越多个字线的多个源极捆扎带，多个源极捆扎线连接到多个源极区域和导电线路中的至少一个。 半导体器件还包括连接到导线的接地线。

    Method and system for vertical DMOS with slots
    57.
    发明授权
    Method and system for vertical DMOS with slots 有权
    垂直DMOS与插槽的方法和系统

    公开(公告)号：US07087491B1

    公开(公告)日：2006-08-08

    申请号：US10376773

    申请日：2003-02-28

    Applicant: John Durbin Husher

    Inventor： John Durbin Husher

    IPC: H01L21/336

    CPC classification number: H01L21/743 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7813 ,  Y10S257/909

    Abstract: A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies.

    Abstract translation: 公开了一种用于提供高功率，低电阻，高效率的垂直DMOS器件的方法。 该方法包括提供其上具有源体结构的半导体衬底。 该方法还包括在源/体结构中提供多个槽，并在多个槽内提供金属以形成多个结构。 公开了一种开槽的PowerFET阵列。 这种开槽方法导致密集的PowerFET，由于开槽设计而导致的低Ron，氧化物隔离工艺，除了槽之外没有任何额外的步骤，较低的电容，较低的泄漏，更小的管芯，改善的热传递，改善的电迁移， 降低接地电阻，减少串扰，降低隔离扩散和沉降扩散，多为低温处理，并提供单金属加工双金属。 还公开了一种用于将该垂直DMOS与CMOS，双极和BCD集成的方法，以使用掩埋功率总线方法和这些技术来提供优化的小型高效晶片。

    Line layout structure of semiconductor memory device
    59.
    发明申请
    Line layout structure of semiconductor memory device 有权
    半导体存储器件的线路布局结构

    公开(公告)号：US20060118958A1

    公开(公告)日：2006-06-08

    申请号：US11281837

    申请日：2005-11-17

    Applicant: Hyang-Ja Yang ,  Kang-Young Kim

    Inventor： Hyang-Ja Yang ,  Kang-Young Kim

    IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC classification number: H01L27/1104 ,  H01L27/11 ,  Y10S257/903 ,  Y10S257/909

    Abstract: A line layout structure comprises first metal lines disposed in a first direction on a cell array region to form first power lines for supplying power to static memory cells, second metal lines disposed over the first metal lines in a second direction substantially perpendicular to the first metal lines to form second power lines for supplying power to the first power lines, third metal lines disposed over the second metal lines to form third power lines for supplying power to the second power lines, and fourth metal lines disposed over the third metal lines to form fourth power lines for supplying power to the third power lines.

    Abstract translation: 线路布置结构包括在单元阵列区域上沿第一方向布置的第一金属线，以形成用于向静态存储单元供电的第一电力线，第二金属线沿着基本垂直于第一金属的第二方向设置在第一金属线上 线形成用于向第一电力线供电的第二电力线，设置在第二金属线上的第三金属线，以形成用于向第二电力线供电的第三电力线，以及设置在第三金属线上的第四金属线，以形成 用于向第三电力线供电的第四电力线。

    Semiconductor memory device and manufacturing method therefor
    60.
    发明申请
    Semiconductor memory device and manufacturing method therefor 有权

    公开(公告)号：US20050230748A1

    公开(公告)日：2005-10-20

    申请号：US11155849

    申请日：2005-06-17

    Applicant: Kenji Saito ,  Hiroshi Furuta

    Inventor： Kenji Saito ,  Hiroshi Furuta

    IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

    CPC classification number: H01L27/11568 ,  G11C16/0475 ,  H01L27/115 ,  Y10S257/90 ,  Y10S257/909

    Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line. A plurality of the aforementioned interconnections are arranged for extending parallel to one another in the memory cell array in an oblique direction relative to the lattice of the first and second electrodes.

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