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    BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE
    2.
    发明申请
    BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE 失效
    具有开口线结构的半导体存储器件的位线检测放大器

    公开(公告)号：US20110103168A1

    公开(公告)日：2011-05-05

    申请号：US12986253

    申请日：2011-01-07

    申请人： Hyang-Ja Yang ,  Su-Yeon Kim

    发明人： Hyang-Ja Yang ,  Su-Yeon Kim

    IPC分类号： G11C7/02

    CPC分类号： G11C7/065 ,  G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/005

    摘要： In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized.

    摘要翻译： 在一个实施例中，具有开放位线结构的半导体存储器件的位线读出放大器包括读出放大器块，第一电压驱动器和第二电压驱动器。 读出放大器块包括第一读出放大器和第二读出放大器，每个读出放大器和第二读出放大器感测并放大位线和互补位线之间的信号差。 第一电压驱动器将电源电压施加到第一读出放大器，并且第二电压驱动器向第二读出放大器施加接地电压。 在布置读出放大器块的位线读出放大器区域中的每两个或更多个读出放大器块设置第一电压驱动器，并且第二电压驱动器被布置在控制电路所在的连接区域中以控制 读出放大器块。 电容噪声和器件尺寸均被最小化。

    Bit line sense amplifier of semiconductor memory device having open bit line structure
    3.
    发明授权
    Bit line sense amplifier of semiconductor memory device having open bit line structure 有权
    具有开放位线结构的半导体存储器件的位线读出放大器

    公开(公告)号：US07639556B2

    公开(公告)日：2009-12-29

    申请号：US11834516

    申请日：2007-08-06

    申请人： Hyang-Ja Yang ,  Su-Yeon Kim

    发明人： Hyang-Ja Yang ,  Su-Yeon Kim

    IPC分类号： G11C7/02 ,  G11C5/06 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/005

    摘要： In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized.

    摘要翻译： 在一个实施例中，具有开放位线结构的半导体存储器件的位线读出放大器包括读出放大器块，第一电压驱动器和第二电压驱动器。 读出放大器块包括第一读出放大器和第二读出放大器，每个读出放大器和第二读出放大器感测并放大位线和互补位线之间的信号差。 第一电压驱动器将电源电压施加到第一读出放大器，并且第二电压驱动器向第二读出放大器施加接地电压。 在布置读出放大器块的位线读出放大器区域中的每两个或更多个读出放大器块设置第一电压驱动器，并且第二电压驱动器被布置在控制电路所在的连接区域中以控制 读出放大器块。 电容噪声和器件尺寸均被最小化。

    CIRCUIT WIRING LAYOUT IN SEMICONDUCTOR MEMORY DEVICE AND LAYOUT METHOD
    4.
    发明申请
    CIRCUIT WIRING LAYOUT IN SEMICONDUCTOR MEMORY DEVICE AND LAYOUT METHOD 审中-公开
    半导体存储器件和布局方法中的电路布线

    公开(公告)号：US20090262564A1

    公开(公告)日：2009-10-22

    申请号：US12491724

    申请日：2009-06-25

    申请人： Hyang-Ja Yang ,  Song-Ja Lee

    发明人： Hyang-Ja Yang ,  Song-Ja Lee

    IPC分类号： G11C5/02 ,  G11C5/06

    CPC分类号： G11C11/417 ,  G11C5/063 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

    摘要： An improved circuit wiring layout provides smooth circuit wiring in a peripheral circuit region adjacent to a memory cell region of a semiconductor memory device, and eliminates a write-speed limiting factor. Forming a metal (instead of a metal silicided polysilicon) wiring layer to be connected to a gate layer, to transmit an electrical signal to the gates of FET (e.g., MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors formed in the peripheral circuit region; the metal wiring layer is formed (e.g., using one metal damascene process), on a layer different from a word line layer formed on the gate layer (e.g., using another metal damascene process), thereby obtaining a layout of a peripheral circuit region having a reduced area and without using a silicide process.

    摘要翻译： 改进的电路布线布局在与半导体存储器件的存储单元区域相邻的外围电路区域中提供平滑的电路布线，并且消除了写入速度限制因素。 形成要连接到栅极层的金属（代替金属硅化多晶硅）布线层，以将电信号传输到FET（例如，形成在外围电路区域中的MOSFET（金属氧化物半导体场效应晶体管））的栅极 在与栅极层上形成的字线层不同的层（例如，使用其他金属镶嵌工艺）上形成金属布线层（例如，使用一个金属镶嵌工艺），从而获得外围电路区域的布局 具有减小的面积并且不使用硅化物工艺。

    Layout structure of MOS transistors on an active region
    5.
    发明授权
    Layout structure of MOS transistors on an active region 失效
    有源区MOS晶体管的布局结构

    公开(公告)号：US07525173B2

    公开(公告)日：2009-04-28

    申请号：US11485341

    申请日：2006-07-13

    申请人： Hyang-Ja Yang ,  Su-Jin Park ,  Uk-Rae Cho ,  Sung-Hoon Kim

    发明人： Hyang-Ja Yang ,  Su-Jin Park ,  Uk-Rae Cho ,  Sung-Hoon Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L27/0203 ,  H01L21/823418 ,  H01L21/823481

    摘要： In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.

    摘要翻译： 在多个金属氧化物半导体（MOS）晶体管的布局结构中，布局结构可以包括具有第一漏极区域的第一组MOS晶体管和分别分配给与所有侧面隔离的组有源区域的第一源极区域 通过沟槽隔离，以及第二组MOS晶体管，其具有分配给组有源区的第二漏极区和第二源极区。 第二组布置在第一组与组有源区的边缘之间。 第一漏极区域和第一源极区域中的一个或两个不与指状栅电极的长度方向上的沟槽隔离边缘接触。

    Semiconductor memory device and layout method thereof
    6.
    发明申请
    Semiconductor memory device and layout method thereof 有权
    半导体存储器件及其布局方法

    公开(公告)号：US20090059687A1

    公开(公告)日：2009-03-05

    申请号：US12230570

    申请日：2008-09-02

    申请人： Hyang-Ja Yang ,  Wol-Jin Lee

    发明人： Hyang-Ja Yang ,  Wol-Jin Lee

    IPC分类号： G11C7/00 ,  G11C7/12

    CPC分类号： G11C7/12 ,  G11C7/18

    摘要： Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including an efficient layout circuit and method thereof. The method may include sharing a first active area between a first precharger and a second precharger and sharing a second active area between a third precharger and a fourth precharger. The semiconductor memory device may include a level shifter configured to receive a first precharge control signal and boost a logic high level of the first precharge control signal to an external power supply voltage level to output a boosted first precharge control signal. The semiconductor memory device may further include first, second, third and fourth prechargers. The first and third prechargers may be configured to precharge data signals transmitted to a first and second pair of local input/output data lines to the first precharge voltage in response to the boosted first precharge control signal during a data read operation.

    摘要翻译： 示例性实施例涉及半导体存储器件，例如包括有效布局电路的半导体存储器件及其方法。 该方法可以包括在第一预充电器和第二预充电器之间共享第一有效区域并且在第三预充电器和第四预充电器之间共享第二有效区域。 半导体存储器件可以包括电平移位器，其被配置为接收第一预充电控制信号并将第一预充电控制信号的逻辑高电平升高到外部电源电压电平以输出升压的第一预充电控制信号。 半导体存储器件还可以包括第一，第二，第三和第四预充电器。 第一和第三预充电器可以被配置为在数据读取操作期间响应于升压的第一预充电控制信号而将传输到第一和第二对本地输入/输出数据线的数据信号预充电到第一预充电电压。

    BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE
    7.
    发明申请
    BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE 有权
    具有开口线结构的半导体存储器件的位线检测放大器

    公开(公告)号：US20080049528A1

    公开(公告)日：2008-02-28

    申请号：US11834516

    申请日：2007-08-06

    申请人： Hyang-Ja YANG ,  Su-Yeon KIM

    发明人： Hyang-Ja YANG ,  Su-Yeon KIM

    IPC分类号： G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/005

    摘要： In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized.

    摘要翻译： 在一个实施例中，具有开放位线结构的半导体存储器件的位线读出放大器包括读出放大器块，第一电压驱动器和第二电压驱动器。 读出放大器块包括第一读出放大器和第二读出放大器，每个读出放大器和第二读出放大器感测并放大位线和互补位线之间的信号差。 第一电压驱动器将电源电压施加到第一读出放大器，并且第二电压驱动器向第二读出放大器施加接地电压。 在布置读出放大器块的位线读出放大器区域中的每两个或更多个读出放大器块设置第一电压驱动器，并且第二电压驱动器被布置在控制电路所在的连接区域中以控制 读出放大器块。 电容噪声和器件尺寸均被最小化。

    Semiconductor device having function of improved electrostatic discharge protection
    8.
    发明申请
    Semiconductor device having function of improved electrostatic discharge protection 有权
    具有改善的静电放电保护功能的半导体器件

    公开(公告)号：US20070215948A1

    公开(公告)日：2007-09-20

    申请号：US11522886

    申请日：2006-09-18

    申请人： Hyang-Ja Yang

    发明人： Hyang-Ja Yang

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0255 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

    摘要： A semiconductor device includes a diode region having a plurality of protection diodes and a pad region overlapped with an upper part of the diode region. The pad region having a pad installed corresponding to an external connection terminal. The semiconductor device further includes a contact plug unit which connects at least one of a plurality of active regions constituting the diode region and the pad within the diode region.

    摘要翻译： 半导体器件包括具有多个保护二极管的二极管区域和与二极管区域的上部重叠的焊盘区域。 所述垫区域具有与外部连接端子对应地安装的垫。 半导体器件还包括接触插头单元，其连接构成二极管区域的多个有源区域和二极管区域内的焊盘中的至少一个。

    Line layout structure of semiconductor memory devices
    9.
    发明申请
    Line layout structure of semiconductor memory devices 有权
    半导体存储器件的线路布局结构

    公开(公告)号：US20060059449A1

    公开(公告)日：2006-03-16

    申请号：US11227563

    申请日：2005-09-15

    申请人： Hyang-Ja Yang ,  Yun-Jin Jo

    发明人： Hyang-Ja Yang ,  Yun-Jin Jo

    IPC分类号： G06F17/50

    CPC分类号： G11C5/063 ,  H01L27/1104

    摘要： A line layout structure of semiconductor memory device comprises first metal wire lines forming a bit line coupled to a memory cell, second metal wire lines disposed substantially orthogonal to the first metal wire lines and over the first metal wire lines, the second metal wire lines forming a section word line electrically coupled to the memory cell, and third metal wire lines disposed substantially parallel to the second metal wire lines and over the second metal wire lines, the third metal wire lines forming a first power line or signal line.

    摘要翻译： 半导体存储器件的线路布局结构包括形成耦合到存储单元的位线的第一金属线线，与第一金属线线基本上正交并且与第一金属线线基本正交的第二金属线线，第二金属线线形成 电耦合到所述存储单元的部分字线以及基本上平行于所述第二金属线线设置并且在所述第二金属线路上的第三金属线线，所述第三金属线线形成第一电力线或信号线。

    Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits
    10.
    发明授权
    Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits 有权
    具有用于测试存储器阵列和外围电路的内部电压发生器的半导体存储器件

    公开(公告)号：US06958947B2

    公开(公告)日：2005-10-25

    申请号：US10359075

    申请日：2003-02-06

    申请人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

    发明人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

    IPC分类号： G11C5/14 ,  G11C29/12 ,  G11C29/50

    CPC分类号： G11C29/12005 ,  G11C5/147 ,  G11C11/41 ,  G11C29/12 ,  G11C29/50 ,  G11C2207/2254

    摘要： A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.

    摘要翻译： 一种半导体存储器件，包括用于调节外部电源电压并产生第一和第二内部电源电压的内部电压发生器电路。 第一内部电源电压经由第一电源线提供给存储单元阵列，并且第二内部电源电压经由第二电源线提供给外围电路。 控制电路控制内部电压发生器电路，使得第一和第二内部电源电压的电平根据操作模式而变化。