公开(公告)号：US09058878B2

公开(公告)日：2015-06-16

申请号：US13341303

申请日：2011-12-30

Applicant: Seiichi Aritome ,  Soon Ok Seo

Inventor： Seiichi Aritome ,  Soon Ok Seo

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/26

Abstract: A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation on first cells next to the target cells along a first direction if, as a result of the read operation on the target cells, error correction is unfeasible, performing the read operation again on the target cells by selecting one of a plurality of read voltages in response to a result of the read operation on the first cells and by using the selected read voltage for reading data of the target cells, and terminating the read operation on the target cells if error correction is feasible.

Abstract translation: 半导体存储器件的读取方法包括通过使用第一读取电压对目标单元执行读取操作，如果作为对目标单元的读取操作的结果，错误校正是可行的，则终止对目标单元的读取操作， 如果作为对目标单元的读取操作的结果，误差校正是不可行的，则对目标单元的旁边的第一单元执行读取操作，通过选择多个目标单元之一对目标单元执行再次操作 的读取电压，并且通过使用所选择的读取电压来读取目标单元的数据，并且如果纠错是可行的，则终止对目标单元的读取操作。

公开(公告)号：US09019767B2

公开(公告)日：2015-04-28

申请号：US13398397

申请日：2012-02-16

Applicant: Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

Inventor： Seiichi Aritome ,  Hyun-Seung Yoo ,  Sung-Jin Whang

IPC: G11C16/04 ,  H01L27/115 ,  G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0408 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract translation: 非易失性存储器件包括从衬底垂直延伸的沟道，沿着沟道堆叠的多个存储单元; 连接到所述沟道的第一端部的源极区域和与所述沟道的第二端部连接的位线，其中与所述源极区域相邻的所述沟道的所述第一端部形成为未掺杂的半导体层或半导体 层掺杂有P型杂质。

公开(公告)号：US08705287B2

公开(公告)日：2014-04-22

申请号：US13282029

申请日：2011-10-26

Applicant: Seiichi Aritome ,  Soo Jin Wi ,  Angelo Visconti ,  Mattia Robustelli

Inventor： Seiichi Aritome ,  Soo Jin Wi ,  Angelo Visconti ,  Mattia Robustelli

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/3459 ,  G11C16/06 ,  G11C16/3454 ,  G11C16/3468

Abstract: A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.

Abstract translation: 一种操作半导体存储器件的方法包括执行第一程序操作以提高存储单元的阈值电压，执行用于检测快速程序存储单元的程序验证操作，每个程序存储单元的阈值电压升高高于第一次验证电压 通过使用目标验证电压和顺序地低于目标验证电压的第一子验证电压和第二子验证电压，从第二子验证电压或更低的次级验证电压进行第二子验证电压，并且在 低于目标验证电压的存储单元的每个阈值电压的增量大于每个快速程序存储单元的阈值电压的增量。

公开(公告)号：US20130128660A1

公开(公告)日：2013-05-23

申请号：US13475204

申请日：2012-05-18

Applicant: Hyun-Seung YOO ,  Sung-Joo HONG ,  Seiichi ARITOME ,  Seok-Kiu LEE ,  Sung-Kye PARK ,  Gyu-Seog CHO ,  Eun-Seok CHOI ,  Han-Soo JOO

Inventor： Hyun-Seung YOO ,  Sung-Joo HONG ,  Seiichi ARITOME ,  Seok-Kiu LEE ,  Sung-Kye PARK ,  Gyu-Seog CHO ,  Eun-Seok CHOI ,  Han-Soo JOO

IPC: G11C16/04 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/26 ,  G11C16/3418

Abstract: A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

Abstract translation: 一种非易失性存储器件的读取方法，包括分别包括一个浮动栅极和两个控制栅极的多个存储器单元，两个控制栅极分别与浮置栅极的两个交替侧相邻设置，并且两个相邻的存储单元共享一个 所述读取方法包括将读取电压施加到所选择的存储器单元的控制栅极，将第二通过电压施加到与所选择的存储器单元的控制栅极不同的存储单元的控制栅极的替代控制栅极，所述存储器单元从控制栅极开始， 所选择的存储单元，以及施加低于第二通过电压的第一通过电压，以从控制栅极开始的第二选择的存储单元开始，将不同于所选存储单元的控制栅极的存储单元的控制栅极交替 。

公开(公告)号：US08441058B2

公开(公告)日：2013-05-14

申请号：US13180361

申请日：2011-07-11

Applicant: Seiichi Aritome

Inventor： Seiichi Aritome

IPC: H01L29/788

CPC classification number: H01L21/762 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.

公开(公告)号：US20130107602A1

公开(公告)日：2013-05-02

申请号：US13601531

申请日：2012-08-31

Applicant: Sang Hyun OH ,  Seiichi Aritome ,  Sang Bum LEE

Inventor： Sang Hyun OH ,  Seiichi Aritome ,  Sang Bum LEE

IPC: H01L27/088 ,  H01L21/336 ,  G11C5/02

CPC classification number: H01L27/11556 ,  G11C16/0408 ,  G11C16/14 ,  H01L21/8221 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

Abstract: A three-dimensional (3-D) nonvolatile memory device includes a channel layer protruded from a substrate, a plurality of memory cells stacked along the channel layer, a source line coupled to the end of one side of the channel layer, a bit line coupled to the end of the other side of the channel layer, a first junction interposed between the end of one side of the channel layer and the source line and configured to have a P type impurity doped therein, and a second junction interposed between the end of the other side of the channel layer and the bit line and configured to have an N type impurity doped therein.

Abstract translation: 三维（3-D）非易失性存储器件包括从衬底突出的沟道层，沿着沟道层堆叠的多个存储单元，耦合到沟道层一侧的端部的源极线，位线 耦合到沟道层的另一侧的端部，插入在沟道层的一侧的端部和源极线之间并且被配置为在其中掺杂有P型杂质的第一结，以及插入在端部之间的第二结 的沟道层的另一侧和位线，并且被配置为在其中掺杂有N型杂质。

公开(公告)号：US08350309B2

公开(公告)日：2013-01-08

申请号：US13310148

申请日：2011-12-02

Applicant: Hiroshi Watanabe ,  Hiroshi Nakamura ,  Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshitake Yaegashi ,  Yuji Takeuchi ,  Kenichi Imamiya ,  Ken Takeuchi ,  Hideko Oodaira

Inventor： Hiroshi Watanabe ,  Hiroshi Nakamura ,  Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshitake Yaegashi ,  Yuji Takeuchi ,  Kenichi Imamiya ,  Ken Takeuchi ,  Hideko Oodaira

IPC: H01L27/108 ,  H01L29/73

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Abstract translation: 选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。 第一级导电层具有接触区域。 第二级导电层的部分被去除，位于接触区域上方。 在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。 一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

公开(公告)号：US08339858B2

公开(公告)日：2012-12-25

申请号：US13285697

申请日：2011-10-31

Applicant: Seiichi Aritome

Inventor： Seiichi Aritome

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: Memory devices and methods of programming memory cells including selecting a voltage to apply to a control gate of the memory cell during programming of a data value of a sense amplifier to the memory cell in response to at least a data value contained in a data latch that is in communication with the sense amplifier.

公开(公告)号：US20120241840A1

公开(公告)日：2012-09-27

申请号：US13402989

申请日：2012-02-23

Applicant: Nam-Jae Lee ,  Seiichi Aritome

Inventor： Nam-Jae Lee ,  Seiichi Aritome

IPC: H01L29/788 ,  H01L21/28

CPC classification number: H01L21/76224 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.

Abstract translation: 非易失性存储器件包括具有由隔离层限定的并且具有从隔离层向上延伸的第一侧壁的有源区的衬底，与有源区相邻的浮动栅极与介于有源区之间的隧道介电层和 浮置栅极并从衬底向上延伸，布置在浮置栅极上的隔间介电层以及设置在栅极间介电层上的控制栅极。

公开(公告)号：US08264879B2

公开(公告)日：2012-09-11

申请号：US12948469

申请日：2010-11-17

Applicant: Seiichi Aritome

Inventor： Seiichi Aritome

IPC: G11C16/04

CPC classification number: G11C16/349 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

Abstract: Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the memory cells to one of a number of states. Operating memory cells also includes programming at least another one of the memory cells, which is adjacent to the programmed at least one of the memory cells, to one of a different number of states. Operating memory cells also includes sensing non-erased states of the memory cells using at least one common voltage level.

Abstract translation: 教授了用于操作存储器单元的方法，设备，模块和系统。 用于操作存储器单元的方法包括将至少一个存储器单元编程为多个状态之一。 操作存储器单元还包括将与编程的至少一个存储器单元相邻的存储单元中的至少另一个存储器编程为不同数量的状态之一。 操作存储单元还包括使用至少一个公共电压电平来感测存储器单元的未擦除状态。