公开(公告)号：US08809128B2

公开(公告)日：2014-08-19

申请号：US12911900

申请日：2010-10-26

Applicant: Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

IPC: H01L21/82 ,  H01L27/24

CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.

Abstract translation: 本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。 存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。 公开了许多附加方面。

公开(公告)号：US20110095438A1

公开(公告)日：2011-04-28

申请号：US12911900

申请日：2010-10-26

Applicant: Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

IPC: H01L23/522 ,  H01L21/768

CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.

Abstract translation: 本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。 存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。 公开了许多附加方面。

公开(公告)号：US08741696B2

公开(公告)日：2014-06-03

申请号：US12911944

申请日：2010-10-26

Applicant: Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

IPC: H01L21/82

CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

Abstract translation: 本发明提供用于制造存储器结构的装置，方法和系统，该方法使用顺序侧壁图案化形成用于存储单元的支柱。 本发明包括从设置在存储层堆叠上方的第一模板层形成第一特征; 形成邻近所述第一特征的第一侧壁间隔物; 通过使用第一侧壁间隔物作为硬掩模形成在掩模层中沿第一方向延伸的第二特征; 在掩模层上沉积第二模板层; 从第二模板层形成第三特征; 形成邻近所述第三特征的第二侧壁间隔物; 并且通过使用第二侧壁间隔件作为硬掩模形成在掩模层中沿第二方向延伸的第四特征。 公开了许多附加方面。

公开(公告)号：US20110095338A1

公开(公告)日：2011-04-28

申请号：US12911944

申请日：2010-10-26

Applicant: Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

IPC: H01L27/08 ,  G03F1/00

CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

Abstract translation: 本发明提供用于制造存储器结构的装置，方法和系统，该方法使用顺序侧壁图案化形成用于存储单元的支柱。 本发明包括从设置在存储层堆叠上方的第一模板层形成第一特征; 形成邻近所述第一特征的第一侧壁间隔物; 通过使用第一侧壁间隔物作为硬掩模形成在掩模层中沿第一方向延伸的第二特征; 在掩模层上沉积第二模板层; 从第二模板层形成第三特征; 形成邻近所述第三特征的第二侧壁间隔物; 并且通过使用第二侧壁间隔件作为硬掩模形成在掩模层中沿第二方向延伸的第四特征。 公开了许多附加方面。

公开(公告)号：US08679967B2

公开(公告)日：2014-03-25

申请号：US12911887

申请日：2010-10-26

Applicant: Roy E. Scheuerlein ,  Yoichiro Tanaka

Inventor： Roy E. Scheuerlein ,  Yoichiro Tanaka

IPC: H01L21/4763

CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

Abstract translation: 本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。 本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁 靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。 公开了许多附加方面。

公开(公告)号：US20110095434A1

公开(公告)日：2011-04-28

申请号：US12911887

申请日：2010-10-26

Applicant: Roy E. Scheuerlein ,  Yoichiro Tanaka

Inventor： Roy E. Scheuerlein ,  Yoichiro Tanaka

IPC: H01L23/48 ,  H01L21/28

CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

Abstract translation: 本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。 本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁 靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。 公开了许多附加方面。

公开(公告)号：US20110178265A1

公开(公告)日：2011-07-21

申请号：US13121350

申请日：2009-08-18

Applicant: Yoichiro Tanaka ,  Eri Hatano ,  Keisuke Honda

Inventor： Yoichiro Tanaka ,  Eri Hatano ,  Keisuke Honda

IPC: C08G63/85 ,  C07F7/28

CPC classification number: D01F6/62 ,  C08G63/183 ,  C08G63/85

Abstract: Provided are a polyester polymerization catalyst with which the generation of foreign materials caused by the catalyst or mold pollution at the time of molding are reduced and polyesters having remarkably superior thermal stability and color tone can be obtained.Provided is a polyester polymerization catalyst produced by the reaction of a titanium compound and a mannitol in a molar ratio of titanium atom to mannitol of from 1:1 to 1:3. A method for producing a polyester employs the polyester polymerization catalyst.

Abstract translation: 提供一种聚酯聚合催化剂，其在模塑时由催化剂或模具污染引起的异物的产生减少，并且可以获得具有非常优异的热稳定性和色调的聚酯。 提供了通过钛化合物和甘露醇与钛原子与甘露醇的摩尔比为1:1至1:3的反应制备的聚酯聚合催化剂。 聚酯的制造方法采用聚酯聚合催化剂。

公开(公告)号：US20110014779A1

公开(公告)日：2011-01-20

申请号：US12458543

申请日：2009-07-15

Applicant: Raghuveer S. Makala ,  Vance Dunton ,  Yoichiro Tanaka ,  Steven Maxwell ,  Tong Zhang ,  Steven J. Radigan

Inventor： Raghuveer S. Makala ,  Vance Dunton ,  Yoichiro Tanaka ,  Steven Maxwell ,  Tong Zhang ,  Steven J. Radigan

IPC: H01L21/20

CPC classification number: H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

Abstract: A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.

公开(公告)号：US07277262B2

公开(公告)日：2007-10-02

申请号：US10932338

申请日：2004-09-02

Applicant: Masayuki Takagishi ,  Tomomi Funayama ,  Yoichiro Tanaka

Inventor： Masayuki Takagishi ,  Tomomi Funayama ,  Yoichiro Tanaka

IPC: G11B5/39

CPC classification number: G11B5/3912

Abstract: A magnetic recording/reproducing apparatus has a magnetoresistive head having a magnetoresistive film through which a current is flowed in a direction substantially perpendicular to a film plane and a pair of magnetic shields disposed to sandwich the magnetoresistive film, and a preamplifier which supplies a sense current to the magnetoresistive head in constant-current driving.

Abstract translation: 磁记录/再现装置具有磁阻头，该磁阻头具有磁阻膜，电流沿着基本上垂直于膜平面的方向流动，一对磁屏蔽设置成夹在磁阻膜上，前置放大器提供感测电流 到恒流驱动中的磁阻头。

公开(公告)号：US20060047505A1

公开(公告)日：2006-03-02

申请号：US11215016

申请日：2005-08-31

Applicant: Takafumi Kikuchi ,  Yoichiro Tanaka

Inventor： Takafumi Kikuchi ,  Yoichiro Tanaka

IPC: G10L11/00

CPC classification number: H04M1/19 ,  H04M1/0214

Abstract: A disk device and microphone are arranged in a device main body. The case of the disk device includes a first shell having a bottom, and a second shell having a top cover. A disk-shaped recording medium is contained in the case. The microphone is positioned closer to the top cover of the disk device than to the bottom of the disk device in the thickness direction of the device main body. Assuming that θ represents the angle between straight line connecting the disk device to the microphone by the most direct way, and a plane parallel to a surface of the top cover of the disk device, the disk device and microphone arranged to satisfy the following relationship with respect to the maximum deformation angle α of the top cover of the disk device in a lowest-order vibration mode: 0≦θ

Abstract translation: 磁盘设备和麦克风被布置在设备主体中。 盘装置的情况包括具有底部的第一壳体和具有顶盖的第二壳体。 壳体内装有盘状的记录介质。 在设备主体的厚度方向上，麦克风位于比盘装置的顶盖更靠近盘装置的顶盖的位置。 假设θ表示通过最直接方式连接盘装置与麦克风的直线之间的角度，以及平行于盘装置顶盖表面的平面，该盘装置和麦克风被设置为满足以下关系： 相对于最低阶振动模式的盘装置的顶盖的最大变形角α：0 <θ<90°-α。