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    Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning
    1.
    发明授权
    Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning 有权
    使用双侧壁图案形成存储器线和结构的装置和方法，用于四次半间距浮雕图案化

    公开(公告)号：US08679967B2

    公开(公告)日：2014-03-25

    申请号：US12911887

    申请日：2010-10-26

    Applicant: Roy E. Scheuerlein ,  Yoichiro Tanaka

    Inventor： Roy E. Scheuerlein ,  Yoichiro Tanaka

    IPC: H01L21/4763

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

    Abstract translation: 本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。 本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁 靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。 公开了许多附加方面。

    APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING
    2.
    发明申请
    APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING 有权
    使用双重格式化方式形成记忆线和结构的四种方法的设备和方法

    公开(公告)号：US20110095434A1

    公开(公告)日：2011-04-28

    申请号：US12911887

    申请日：2010-10-26

    Applicant: Roy E. Scheuerlein ,  Yoichiro Tanaka

    Inventor： Roy E. Scheuerlein ,  Yoichiro Tanaka

    IPC: H01L23/48 ,  H01L21/28

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

    Abstract translation: 本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。 本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁 靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。 公开了许多附加方面。

    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning
    3.
    发明授权
    Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning 有权
    用于三维矩阵阵列存储器布局的方法和装置，用于降低成本图案化

    公开(公告)号：US08809128B2

    公开(公告)日：2014-08-19

    申请号：US12911900

    申请日：2010-10-26

    Applicant: Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    IPC: H01L21/82 ,  H01L27/24

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.

    Abstract translation: 本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。 存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。 公开了许多附加方面。

    METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING
    4.
    发明申请
    METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 有权
    用于降低成本花纹的三维矩阵阵列存储器的布局方法和装置

    公开(公告)号：US20110095438A1

    公开(公告)日：2011-04-28

    申请号：US12911900

    申请日：2010-10-26

    Applicant: Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.

    Abstract translation: 本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。 存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。 存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。 存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。 存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。 公开了许多附加方面。

    Methods of forming pillars for memory cells using sequential sidewall patterning
    5.
    发明授权
    Methods of forming pillars for memory cells using sequential sidewall patterning 有权
    使用顺序侧壁图案形成记忆单元柱的方法

    公开(公告)号：US08741696B2

    公开(公告)日：2014-06-03

    申请号：US12911944

    申请日：2010-10-26

    Applicant: Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    IPC: H01L21/82

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

    Abstract translation: 本发明提供用于制造存储器结构的装置，方法和系统，该方法使用顺序侧壁图案化形成用于存储单元的支柱。 本发明包括从设置在存储层堆叠上方的第一模板层形成第一特征; 形成邻近所述第一特征的第一侧壁间隔物; 通过使用第一侧壁间隔物作为硬掩模形成在掩模层中沿第一方向延伸的第二特征; 在掩模层上沉积第二模板层; 从第二模板层形成第三特征; 形成邻近所述第三特征的第二侧壁间隔物; 并且通过使用第二侧壁间隔件作为硬掩模形成在掩模层中沿第二方向延伸的第四特征。 公开了许多附加方面。

    METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING
    6.
    发明申请
    METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING 有权
    使用顺序方向图形成存储器细胞的支架的方法

    公开(公告)号：US20110095338A1

    公开(公告)日：2011-04-28

    申请号：US12911944

    申请日：2010-10-26

    Applicant: Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    Inventor： Roy E. Scheuerlein ,  Christopher J. Petti ,  Yoichiro Tanaka

    IPC: H01L27/08 ,  G03F1/00

    CPC classification number: G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

    Abstract translation: 本发明提供用于制造存储器结构的装置，方法和系统，该方法使用顺序侧壁图案化形成用于存储单元的支柱。 本发明包括从设置在存储层堆叠上方的第一模板层形成第一特征; 形成邻近所述第一特征的第一侧壁间隔物; 通过使用第一侧壁间隔物作为硬掩模形成在掩模层中沿第一方向延伸的第二特征; 在掩模层上沉积第二模板层; 从第二模板层形成第三特征; 形成邻近所述第三特征的第二侧壁间隔物; 并且通过使用第二侧壁间隔件作为硬掩模形成在掩模层中沿第二方向延伸的第四特征。 公开了许多附加方面。

    Optimization of critical dimensions and pitch of patterned features in and above a substrate
    8.
    发明授权
    Optimization of critical dimensions and pitch of patterned features in and above a substrate 有权
    优化衬底中和图案上的图案特征的临界尺寸和间距

    公开(公告)号：US08766332B2

    公开(公告)日：2014-07-01

    申请号：US13613956

    申请日：2012-09-13

    Applicant: James M. Cleeves ,  Roy E. Scheuerlein

    Inventor： James M. Cleeves ,  Roy E. Scheuerlein

    IPC: H01L29/80

    CPC classification number: H01L27/105 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.

    Abstract translation: 在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。 本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。 存储器阵列的一个级别包括例如平行轨道和扇出区域。 希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。 这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在 轨道，并且在不太关键的扇出区域更放松。

    Cross point non-volatile memory cell
    9.
    发明授权
    Cross point non-volatile memory cell 有权
    交叉点非易失性存储单元

    公开(公告)号：US08605486B2

    公开(公告)日：2013-12-10

    申请号：US13591097

    申请日：2012-08-21

    Applicant: Roy E. Scheuerlein

    Inventor： Roy E. Scheuerlein

    IPC: G11C11/21

    CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

    Abstract: A memory system includes an X line, a first Y line, a second Y line, a semiconductor region of a first type running along the X line, first switching material and a first semiconductor region of a second type between the first Y line and the semiconductor region of the first type, second switching material and a second semiconductor region of the second type between the second Y line and the semiconductor region of the first type, and control circuitry. The control circuitry changes the programming state of the first switching material to a first state by causing a first current to flow from the second Y line to the first Y line through the first switching material, the second switching material, the semiconductor region of the first type, the first semiconductor region of the second type and the second semiconductor region of the second type.

    Abstract translation: 存储系统包括X线，第一Y线，第二Y线，沿着X线延伸的第一类型的半导体区域，第一开关材料和第一Y线与第一Y线之间的第二类型的第一半导体区域 第一类型的半导体区域，第二开关材料和第二类型的第二类型的第二半导体区域在第二Y线和第一类型的半导体区域之间，以及控制电路。 控制电路通过使第一电流从第二Y线流过第一Y线，通过第一开关材料，第二开关材料，第一开关材料的半导体区域，将第一开关材料的编程状态改变到第一状态 第二类型的第一半导体区域和第二类型的第二半导体区域。

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