公开(公告)号：US08372740B2

公开(公告)日：2013-02-12

申请号：US13366916

申请日：2012-02-06

Applicant: Huiwen Xu ,  Yung-Tin Chen ,  Steven J. Radigan

Inventor： Huiwen Xu ,  Yung-Tin Chen ,  Steven J. Radigan

IPC: H01L21/44

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/101 ,  H01L27/1021

Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.

Abstract translation: 实施例通常涉及制造半导体器件的方法，更具体地，涉及制造半导体柱结构的方法以及使用选择性或方向性间隙填充来增加阵列特征图案密度。 该技术可应用于各种材料，可应用于制作单片二维或三维存储阵列。

公开(公告)号：US07982273B2

公开(公告)日：2011-07-19

申请号：US12470886

申请日：2009-05-22

Applicant: Yung-Tin Chen ,  Christopher J. Petti ,  Steven J. Radigan ,  Tanmay Kumar

Inventor： Yung-Tin Chen ,  Christopher J. Petti ,  Steven J. Radigan ,  Tanmay Kumar

IPC: H01L29/76

CPC classification number: H01L27/0688 ,  G03F7/70633 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described.

Abstract translation: 单片三维半导体器件结构包括第一层，其包括在第一位置处的第一参考标记的第一次出现，以及包括在第二位置处的第二参考标记的第二次出现的第二层，其中第二位置基本上直接 在第一个位置以上。 所述器件结构还包括在所述第一层和所述第二层之间的中间层，所述中间层包括阻挡结构，其中所述阻挡结构垂直插入所述第一参考标记的第一次出现和所述第一参考标记的第二次出现之间 。 还描述了其他方面。

公开(公告)号：US07923305B1

公开(公告)日：2011-04-12

申请号：US12686201

申请日：2010-01-12

Applicant: Natalie Nguyen ,  Paul Wai Kie Poon ,  Steven J. Radigan ,  Michael Konevecki ,  Yung-Tin Chen

Inventor： Natalie Nguyen ,  Paul Wai Kie Poon ,  Steven J. Radigan ,  Michael Konevecki ,  Yung-Tin Chen

IPC: H01L21/82

CPC classification number: H01L27/101 ,  H01L21/0337 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/1675

Abstract: A method of making a device includes forming a first sacrificial layer over an underlying layer, forming a first photoresist layer over the first sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, etching the first sacrificial layer using both the first and the second photoresist features as a mask to form first sacrificial features, forming a spacer layer over the first sacrificial features, etching the spacer layer to form spacer features and to expose the sacrificial features, removing the first sacrificial features, and etching at least part of the underlying layer using the spacer features as a mask.

Abstract translation: 制造器件的方法包括在下层上形成第一牺牲层，在第一牺牲层上形成第一光致抗蚀剂层，使第一光致抗蚀剂层形成图形以形成第一光致抗蚀剂特征，使第一光致抗蚀剂特征不溶于溶剂，形成 在第一光致抗蚀剂特征上的第二光致抗蚀剂层，图案化第二光致抗蚀剂层以形成第二光致抗蚀剂特征，使用第一和第二光致抗蚀剂特征作为掩模蚀刻第一牺牲层以形成第一牺牲特征， 第一牺牲特征，蚀刻间隔层以形成间隔物特征并暴露牺牲特征，去除第一牺牲特征，以及使用间隔物特征作为掩模来蚀刻至少部分下层。

公开(公告)号：US07786015B2

公开(公告)日：2010-08-31

申请号：US12149151

申请日：2008-04-28

Applicant: Yung-Tin Chen ,  Chun-Ming Wang ,  Steven J. Radigan ,  Christopher J. Petti ,  Steven Maxwell

Inventor： Yung-Tin Chen ,  Chun-Ming Wang ,  Steven J. Radigan ,  Christopher J. Petti ,  Steven Maxwell

IPC: H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1021

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.

Abstract translation: 制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔的特征，在所述至少两个特征上形成侧壁间隔物，选择性地去除间隔开的特征， 用填料特征填充第一侧壁间隔物和第二侧壁间隔物之间​​的空间，选择性地去除侧壁间隔物以留下彼此间隔开的多个填料特征，并使用填料特征来蚀刻至少一个器件层，如 一个面具

公开(公告)号：US07754605B2

公开(公告)日：2010-07-13

申请号：US11478706

申请日：2006-06-30

Applicant: S. Brad Herner ,  Steven J Radigan

Inventor： S. Brad Herner ,  Steven J Radigan

IPC: H01L21/443

CPC classification number: H01L27/1021 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/2254

Abstract: The surface of a conductive layer such as a conductive nitride, a conductive silicide, a metal, or metal alloy or compound, is exposed to a dopant gas which provides an n-type or p-type dopant. The dopant gas may be included in a plasma. Semiconductor material, such as silicon, germanium, or their alloys, is deposited directly on the surface which has been exposed to the dopant gas. During and subsequent to deposition, dopant atoms diffuse into the deposited semiconductor, forming a thin heavily doped region and making a good ohmic contact between the semiconductor material and the underlying conductive layer.

Abstract translation: 诸如导电氮化物，导电硅化物，金属或金属合金或化合物的导电层的表面暴露于提供n型或p型掺杂剂的掺杂气体。 掺杂气体可以包括在等离子体中。 诸如硅，锗或其合金的半导体材料直接沉积在暴露于掺杂气体的表面上。 在沉积期间和之后，掺杂剂原子扩散到沉积的半导体中，形成薄的重掺杂区域，并在半导体材料和下面的导电层之间形成良好的欧姆接触。

公开(公告)号：US20090269932A1

公开(公告)日：2009-10-29

申请号：US12149151

申请日：2008-04-28

Applicant: Yung-Tin Chen ,  Chun-Ming Wang ,  Steven J. Radigan ,  Christopher J. Petti ,  Steven Maxwell

Inventor： Yung-Tin Chen ,  Chun-Ming Wang ,  Steven J. Radigan ,  Christopher J. Petti ,  Steven Maxwell

IPC: H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1021

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.

Abstract translation: 制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔的特征，在所述至少两个特征上形成侧壁间隔物，选择性地去除间隔开的特征， 用填料特征填充第一侧壁间隔物和第二侧壁间隔物之间​​的空间，选择性地去除侧壁间隔物以留下彼此间隔开的多个填料特征，并使用填料特征来蚀刻至少一个器件层，如 一个面具

公开(公告)号：US07560339B2

公开(公告)日：2009-07-14

申请号：US11866403

申请日：2007-10-02

Applicant: S. Brad Herner ,  Steven J. Radigan

Inventor： S. Brad Herner ,  Steven J. Radigan

IPC: H01L29/80

CPC classification number: G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/1021 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/868

Abstract: A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.

Abstract translation: 根据本发明的非易失性存储单元包括底部导体，半导体柱和顶部导体。 半导体柱包括结二极管，其包括底部重掺杂区域，中间固有或轻掺杂区域和顶部重掺杂区域，其中顶部和底部重掺杂区域的导电类型相反。 结二极管是垂直取向的，并且具有降低的高度，在约500埃至约3500埃之间。 可以形成这样的单元的单片三维存储器阵列，其包括多个存储器级，电平彼此整体地形成。

公开(公告)号：US20090085087A1

公开(公告)日：2009-04-02

申请号：US11863734

申请日：2007-09-28

Applicant: Yoichiro Tanaka ,  Steven J. Radigan ,  Usha Raghuram

Inventor： Yoichiro Tanaka ,  Steven J. Radigan ,  Usha Raghuram

IPC: H01L29/788 ,  H01L21/4763

CPC classification number: H01L27/101 ,  H01L27/1021

Abstract: A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.

Abstract translation: 半导体晶片组件包括电介质基体。 一层硅沉积在其上。 金属硬掩模沉积在硅上。 在金属硬掩模上沉积电介质硬掩模。 光致抗蚀剂沉积在电介质硬掩模上，由此通过光致抗蚀剂从金属硬掩模层形成多个牺牲柱，使得牺牲柱从硅层延伸出来。 界面层设置在导电材料层和硬掩模层之间，以增强多个牺牲柱和导电材料层之间的粘附力，以通过防止多个 牺牲柱由于牺牲柱脱落或脱落而过早地与硅层分离。

公开(公告)号：US20070284656A1

公开(公告)日：2007-12-13

申请号：US11444936

申请日：2006-05-31

Applicant: Steven J. Radigan ,  Usha Raghuram ,  Samuel V. Dunton ,  Michael W. Konevecki

Inventor： Steven J. Radigan ,  Usha Raghuram ,  Samuel V. Dunton ,  Michael W. Konevecki

IPC: H01L29/76 ,  H01L21/8234

CPC classification number: H01L23/5252 ,  H01L27/1021 ,  H01L29/6609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.

Abstract translation: 提供了一种使用导电硬掩模形成图案化特征的方法，其中导电硬掩模在随后的沟槽蚀刻期间保护这些特征以形成提供从上方到那些特征的电连接的大马士革导体。 硬掩模的厚度提供了一个余量，以避免在沟槽蚀刻期间的过蚀刻，这可能对器件性能有害。 该方法有利地用于形成单片三维存储器阵列。

公开(公告)号：US06734620B2

公开(公告)日：2004-05-11

申请号：US10017656

申请日：2001-12-12

Applicant: Steven J. Radigan ,  Matthew A. Bonn ,  Hidenori Kemmotsu ,  Theodore S. Fahlen

Inventor： Steven J. Radigan ,  Matthew A. Bonn ,  Hidenori Kemmotsu ,  Theodore S. Fahlen

IPC: H01J130

CPC classification number: H01J3/022

Abstract: An electron-emitting device (20, 70, 80, or 90) contains an electrode, either a control electrode (38) or an emitter electrode (32), having a specified portion situated off to the side of the bulk of the electrode. For a control electrode, the specified portion is an exposure portion (38EA or 38EB) having openings that expose electron-emissive elements (50A or 50B) situated over an emitter electrode. For an emitter electrode, the specified portion is an emitter-coupling portion situated below at least one electron-emissive element exposed through at least one opening in a control electrode. Configuring the device in this way enables the control-electrode-to-emitter-electrode capacitance to be quite small, thereby enhancing the device's switching speed. If the specified portion of the electrode becomes short circuited to the other electrode, the short-circuit defect can be removed by severing the specified portion from the remainder of its electrode.

Abstract translation: 电子发射器件（20,70,80或90）包含电极，控制电极（38）或发射极（32），其具有位于电极本体侧面的特定部分。 对于控制电极，指定部分是具有露出位于发射极上方的电子发射元件（50A或50B）的开口的曝光部分（38EA或38EB）。 对于发射电极，指定的部分是位于通过控制电极中的至少一个开口暴露的至少一个电子发射元件下方的发射极耦合部分。 以这种方式配置器件使控制电极对发射极之间的电容非常小，从而提高器件的开关速度。 如果电极的指定部分与另一个电极短路，则可以通过从电极的其余部分切断指定部分来消除短路缺陷。