公开(公告)号：US07202150B2

公开(公告)日：2007-04-10

申请号：US11155849

申请日：2005-06-17

Applicant: Kenji Saito ,  Hiroshi Furuta

Inventor： Kenji Saito ,  Hiroshi Furuta

IPC: H01L21/3205

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  H01L27/115 ,  Y10S257/90 ,  Y10S257/909

Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line. A plurality of the aforementioned interconnections are arranged for extending parallel to one another in the memory cell array in an oblique direction relative to the lattice of the first and second electrodes.

Abstract translation: 一种半导体存储器件，适用于通过简化的结构存储能够实现高存储密度的每个单元的多个位，包括沿着一个方向彼此平行延伸的多个第一栅电极和沿着一个方向延伸的多个第二栅电极 与基板表面上的第一和第二电极以矩阵状图案划分的多个部分中的每一个上设置扩散区域的第一栅电极相交的方向。 其中一个划分的四个侧面由两个相邻的第一栅电极和两个相邻的第二栅电极限定，具有四个独立可访问的位，并且通过在分割中的扩散区的接触（CT）连接。 通过接触将多个互连件连接到位于上述对角线的延伸线上的多个矩阵状部分中的其它部分的扩散区域。 多个上述互连布置成相对于第一和第二电极的格子在倾斜方向上在存储单元阵列中彼此平行地延伸。

公开(公告)号：US06936891B2

公开(公告)日：2005-08-30

申请号：US10414720

申请日：2003-04-16

Applicant: Kenji Saito ,  Hiroshi Furuta

Inventor： Kenji Saito ,  Hiroshi Furuta

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  H01L27/115 ,  Y10S257/90 ,  Y10S257/909

Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line. A plurality of the aforementioned interconnections are arranged for extending parallel to one another in the memory cell array in an oblique direction relative to the lattice of the first and second electrodes.

Abstract translation: 一种半导体存储器件，适用于通过简化的结构存储能够实现高存储密度的每个单元的多个位，包括沿着一个方向彼此平行延伸的多个第一栅电极和沿着一个方向延伸的多个第二栅电极 与基板表面上的第一和第二电极以矩阵状图案划分的多个部分中的每一个上设置扩散区域的第一栅电极相交的方向。 其中一个划分的四个侧面由两个相邻的第一栅电极和两个相邻的第二栅电极限定，具有四个独立可访问的位，并且通过在分割中的扩散区的接触（CT）连接。 通过接触将多个互连件连接到位于上述对角线的延伸线上的多个矩阵状部分中的其它部分的扩散区域。 多个上述互连布置成相对于第一和第二电极的格子在倾斜方向上在存储单元阵列中彼此平行地延伸。

公开(公告)号：US20050230748A1

公开(公告)日：2005-10-20

申请号：US11155849

申请日：2005-06-17

Applicant: Kenji Saito ,  Hiroshi Furuta

Inventor： Kenji Saito ,  Hiroshi Furuta

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  H01L27/115 ,  Y10S257/90 ,  Y10S257/909

Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line. A plurality of the aforementioned interconnections are arranged for extending parallel to one another in the memory cell array in an oblique direction relative to the lattice of the first and second electrodes.

公开(公告)号：US08471336B2

公开(公告)日：2013-06-25

申请号：US13437311

申请日：2012-04-02

Applicant: Hiroshi Furuta ,  Shouzou Uchida ,  Muneaki Matsushige ,  Junji Monden

Inventor： Hiroshi Furuta ,  Shouzou Uchida ,  Muneaki Matsushige ,  Junji Monden

IPC: H01L29/76

CPC classification number: H01L27/0207 ,  H01L27/0921 ,  H01L29/0653

Abstract: A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.

Abstract translation: 半导体集成电路器件包括：P沟道MISFET（金属 - 绝缘体 - 半导体场效应晶体管）和N沟道MISFET中的至少一个的栅极电极，其设置在与阱隔离边界相位方向平行的方向上 在所述P沟道MISFET和所述N沟道MISFET之间的第一扩散层具有与设置在两个区域中的多个MISFET中的一个的漏极扩散层相同的导电类型的第一扩散层， MISFET，其分别在与栅电极正交的方向上分离，第二扩散层的导电类型与漏极扩散层的漏极扩散层的导电类型不同，所述漏极扩散层设置在阱隔离边界相之间 以及源极扩散层和漏极扩散层中的一个。

公开(公告)号：US08445951B2

公开(公告)日：2013-05-21

申请号：US13407685

申请日：2012-02-28

Applicant: Hiroshi Furuta ,  Takayuki Shirai ,  Shunsaku Naga

Inventor： Hiroshi Furuta ,  Takayuki Shirai ,  Shunsaku Naga

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L28/90 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1203 ,  H01L29/785

Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.

Abstract translation: 一种半导体集成电路器件，包括：第一电极，包括形成在衬底上的第一半导体层，形成在第一电极的侧表面的至少一部分上的侧表面绝缘膜;形成在第一电极上的上表面绝缘膜 和侧面绝缘膜，覆盖侧面绝缘膜和上表面绝缘膜的第二电极和鳍型场效应晶体管。 第一电极，侧面绝缘膜和第二电极构成电容器元件。 第一电极和第二电极之间的上表面绝缘膜的厚度大于第一电极和第二电极之间的侧表面绝缘膜的厚度，并且鳍式场效应晶体管包括第二半导体层， 相对于基板的平面突出。

公开(公告)号：US08217460B2

公开(公告)日：2012-07-10

申请号：US12801216

申请日：2010-05-27

Applicant: Hiroshi Furuta

Inventor： Hiroshi Furuta

IPC: H01L23/62

CPC classification number: H01L27/1203 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has an SOI (Silicon On Insulator) structure and comprising a P-channel FET and an N-channel FET which are formed on an insulating film. The semiconductor device includes: at least two of first, second, third and fourth PN-junction elements. The first PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of source/drain regions of the P-channel FET and the N-channel FET, respectively. The second PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the source/drain region and a channel region in the P-channel FET, respectively. The third PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of a channel region and the source/drain region in the N-channel FET, respectively. The fourth PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the channel regions of the N-channel FET and the P-channel FET, respectively. At least two PN-junction elements are connected in series in a forward bias between two different terminals to form an electrostatic protection device.

Abstract translation: 半导体器件具有SOI（绝缘体上硅）结构，并且包括形成在绝缘膜上的P沟道FET和N沟道FET。 半导体器件包括：第一，第二，第三和第四PN结元件中的至少两个。 第一PN结元件分别由P型半导体层和具有与P沟道FET和N沟道FET的源/漏区相同的杂质浓度的N型半导体层形成。 第二PN结元件分别由P型半导体层和与P沟道FET中的源/漏区和沟道区相同的杂质浓度的N型半导体层形成。 第三PN结元件由P型半导体层和与N沟道FET中的沟道区和源极/漏极区相同的杂质浓度的N型半导体层分别形成。 第四PN结元件分别由具有与N沟道FET和P沟道FET的沟道区相同的杂质浓度的P型半导体层和N型半导体层形成。 至少两个PN结元件在两个不同端子之间的正向偏压中串联连接以形成静电保护装置。

公开(公告)号：US07981734B2

公开(公告)日：2011-07-19

申请号：US12499559

申请日：2009-07-08

Applicant: Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

Inventor： Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

IPC: H01L21/302

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618

Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.

Abstract translation: 薄膜晶体管的制造方法包括在基板上形成一对源极/漏极，使得源极/漏极在其间限定间隙; 在源/漏电极上形成限定它们之间的间隙的低电阻导电薄膜; 以及在低电阻导电薄膜的上表面和限定在低电阻导电薄膜之间的间隙中形成氧化物半导体薄膜层，使得氧化物半导体薄膜层用作沟道。 蚀刻低电阻导电薄膜和氧化物半导体薄膜层，使得电阻导电薄膜的侧表面和氧化物半导体薄膜层的相应侧表面在沟道的沟道宽度方向上彼此重合。 栅电极安装在氧化物半导体薄膜层上。

公开(公告)号：US07816924B2

公开(公告)日：2010-10-19

申请号：US11870105

申请日：2007-10-10

Applicant: Yukio Kanazawa ,  Masahiro Hanai ,  Hiroshi Furuta

Inventor： Yukio Kanazawa ,  Masahiro Hanai ,  Hiroshi Furuta

IPC: G01R31/327

CPC classification number: H01H1/0015 ,  H01H33/7076 ,  H01H33/901 ,  H01H2001/0026

Abstract: The invention provides a gas insulated switchgear, and a method for detecting arc damage in a part used in a gas insulated switchgear, which detect directly when an electric contact or a peripheral part reaches an initially set wear limit. An insulating nozzle of a circuit breaker contains a marking substance that releases a gaseous substance inside a circuit breaker gas container as a result of wear by an arc. For ensuring heat resistance and insulation properties, the insulating nozzle is ordinarily formed of a fluororesin, but in the present invention, it is formed of the ordinarily used fluororesin having uniformly mixed therein, as the marking substance, a chlorine-containing resin which has excellent heat resistance and insulation properties such as polyvinylidene chloride.

Abstract translation: 本发明提供了一种气体绝缘开关装置，以及用于检测在气体绝缘开关装置中使用的部件中的电弧损伤的方法，其在电接触或周边部分达到初始设定的磨损极限时直接检测。 断路器的绝缘喷嘴包含由于电弧磨损而将断路器气体容器内的气态物质释放的标记物质。 为了确保耐热性和绝缘性，绝缘喷嘴通常由氟树脂形成，但是在本发明中，由通常使用的均匀混合的氟树脂作为标记物质，具有优异的含氯树脂 耐热性和绝缘性能如聚偏二氯乙烯。

公开(公告)号：US20100034039A1

公开(公告)日：2010-02-11

申请号：US12458428

申请日：2009-07-13

Applicant: Kenjyu Shimogawa ,  Hiroshi Furuta

Inventor： Kenjyu Shimogawa ,  Hiroshi Furuta

IPC: G11C7/00

CPC classification number: G11C7/1033 ,  G06F11/1044 ,  G11C7/08 ,  G11C11/4091

Abstract: A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation.

Abstract translation: 半导体集成电路具有耦合到相同字线的存储器单元数量K（K是2个或更多个的自然数），以及耦合到存储单元的多个读出放大器电路。 多个读出放大器电路分为N个（N个是2个以上的自然数）组。 在N个组中，在第一组读出放大器电路被激活并执行预定的读出操作之后，激活第二组读出放大器电路并执行预定的读出操作， 读出放大器电路的第N组顺序地被激活，以执行预定的读出操作。

公开(公告)号：US20070278490A1

公开(公告)日：2007-12-06

申请号：US11809858

申请日：2007-06-01

Applicant: Takashi Hirao ,  Takahiro Hiramatsu ,  Mamoru Furuta ,  Hiroshi Furuta ,  Tokiyoshi Matsuda

Inventor： Takashi Hirao ,  Takahiro Hiramatsu ,  Mamoru Furuta ,  Hiroshi Furuta ,  Tokiyoshi Matsuda

IPC: H01L29/04

CPC classification number: H01L29/7869 ,  H01L29/04 ,  H01L29/045 ,  H01L29/78618

Abstract: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of at least 2.619 Å.

Abstract translation: 半导体器件包括氧化锌的氧化物半导体薄膜层。 氧化物半导体薄膜层的至少一部分的（002）晶格面沿着与半导体器件的衬底垂直的方向具有优选的取向，晶格间距d 002至少为2.619 一个。