Invention Grant
US08471336B2 Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error
失效
包括晶体管的半导体集成电路,其具有形成在元件隔离区域外部的扩散层,以防止软错误
- Patent Title: Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error
- Patent Title (中): 包括晶体管的半导体集成电路,其具有形成在元件隔离区域外部的扩散层,以防止软错误
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Application No.: US13437311Application Date: 2012-04-02
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Publication No.: US08471336B2Publication Date: 2013-06-25
- Inventor: Hiroshi Furuta , Shouzou Uchida , Muneaki Matsushige , Junji Monden
- Applicant: Hiroshi Furuta , Shouzou Uchida , Muneaki Matsushige , Junji Monden
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-134095 20080522; JP2009-096373 20090410
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.
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