公开(公告)号：US07598520B2

公开(公告)日：2009-10-06

申请号：US11809858

申请日：2007-06-01

Applicant: Takashi Hirao ,  Takahiro Hiramatsu ,  Mamoru Furuta ,  Hiroshi Furuta ,  Tokiyoshi Matsuda

Inventor： Takashi Hirao ,  Takahiro Hiramatsu ,  Mamoru Furuta ,  Hiroshi Furuta ,  Tokiyoshi Matsuda

IPC: H01L29/12 ,  H01L31/0256 ,  H01L27/15 ,  H01L23/62

CPC classification number: H01L29/7869 ,  H01L29/04 ,  H01L29/045 ,  H01L29/78618

Abstract: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of at least 2.619 Å.

Abstract translation: 半导体器件包括氧化锌的氧化物半导体薄膜层。 氧化物半导体薄膜层的至少一部分的（002）晶格面沿着与半导体器件的衬底垂直的方向具有优选的取向，晶格间距d002至少为2.619A。

公开(公告)号：US20070187760A1

公开(公告)日：2007-08-16

申请号：US11701343

申请日：2007-02-01

Applicant: Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

Inventor： Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618

Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.

Abstract translation: 薄膜晶体管包括基板和形成在基板上并在其间形成间隙的一对源/漏电极（即源电极和漏电极）。 提供一对低电阻导电薄膜，使得每个涂覆源极/漏极之一的至少一部分。 低电阻导电薄膜在它们之间限定了间隙。 在一对低电阻导电薄膜的上表面上连续地形成氧化物半导体薄膜层，并且沿着限定在低电阻导电薄膜之间的间隙延伸以作为沟道起作用。 氧化物半导体薄膜层的侧表面和低电阻导电薄膜的相应侧表面在沟道的沟道宽度方向上彼此重合。

公开(公告)号：US06420760B2

公开(公告)日：2002-07-16

申请号：US09941980

申请日：2001-08-29

Applicant: Mamoru Furuta ,  Koji Soma

Inventor： Mamoru Furuta ,  Koji Soma

IPC: H01L2362

CPC classification number: H01L29/66757 ,  H01L29/78621

Abstract: A first insulation film is formed as a gate insulation film of a thin film transistor, and a gate electrode is formed on the gate insulation film. Then, dopant is implanted to form source and drain regions. A second insulation film having refractive index n1 and film thickness d2 is formed to cover the first insulation film and gate electrode as an interlayer insulation film. After forming the second insulation film, laser with wavelength &lgr; is applied to activate the dopant. The film thicknesses d1 and d2 of the first and second insulation films satisfy conditions against the laser wavelength &lgr; for forming a reflection protective film at regions where activation is necessary. At the same time, the film thicknesses d1 and d2 are set in a way that the interlayer insulation film on the gate electrode forms a reflective film. This reduces the thermal damage to the gate electrode from the laser during dopant activation.

公开(公告)号：US4579707A

公开(公告)日：1986-04-01

申请号：US508196

申请日：1983-06-27

Applicant: Kazuo Kobayashi ,  Mamoru Furuta ,  Yoshio Maeno

Inventor： Kazuo Kobayashi ,  Mamoru Furuta ,  Yoshio Maeno

IPC: C04B35/622 ,  B28B3/20 ,  B28B11/24 ,  B28B21/52 ,  B28B21/92 ,  C04B35/64

CPC classification number: C04B35/115 ,  B28B11/243 ,  B28B21/52 ,  B28B21/92 ,  C04B35/6263 ,  C04B35/62655 ,  C04B35/6269 ,  C04B35/63488 ,  C04B35/6365 ,  C04B35/64 ,  C04B2235/3206 ,  C04B2235/3418 ,  C04B2235/6021 ,  C04B2235/6581 ,  C04B2235/6582

Abstract: A thin-walled ceramic tube having a high light transmission and high dimens precision, which has been can be used as an envelope for a high pressure lamp, is produced by an extruding process in which a stiff plastic body for extruding is prepared, said body is extruded and the extruded tube is fired, said process being characterized in that the stiff plastic body consists essentially of ceramic raw material, a thermosetting organic substance and water and the extruded tube is hardened by heating immediately after extruded and pressured air is flawed into an inside portion of the extruded tube.

Abstract translation: 通过挤出工序制造已经可以用作高压灯管的透光性和高维度精度的薄壁陶瓷管，其中制备用于挤出的刚性塑料体，所述本体 被挤出并且挤出的管被烧制，所述方法的特征在于，刚性塑料体主要由陶瓷原料，热固性有机物质和水组成，并且挤压管在挤压和加压空气有缺陷之后立即加热硬化 挤出管的内部。

公开(公告)号：US4387067A

公开(公告)日：1983-06-07

申请号：US229503

申请日：1981-01-29

Applicant: Kazuo Kobayashi ,  Mamoru Furuta ,  Yoshio Maeno

Inventor： Kazuo Kobayashi ,  Mamoru Furuta ,  Yoshio Maeno

IPC: H01J9/24 ,  H01J61/30 ,  C04B35/64

CPC classification number: B28B11/008 ,  H01J61/30 ,  H01J9/247

Abstract: The disclosed ceramic arc tube of metal vapor discharge lamps has an arc discharge portion with electrode-holding end portions integrally formed at opposite ends thereof. The outside diameter of the arc discharge portion is larger than that of the electrode-holding end portions. The ceramic arc tube is made by placing a tubular green body in a fusiform cavity of a die, inflating the middle portion of the green body more than end portions thereof, and firing the thus shaped green body.

Abstract translation: 所公开的金属蒸汽放电灯的陶瓷电弧管具有电弧放电部分，其电极保持端部在其相对端整体形成。 电弧放电部的外径大于电极保持端部的外径。 陶瓷电弧管通过将管状生坯体放置在模具的梭状空腔中，使生坯的中部部分比其端部部分膨胀，并且对这样形成的生坯进行烧制而制成。

公开(公告)号：US07977169B2

公开(公告)日：2011-07-12

申请号：US11704838

申请日：2007-02-09

Applicant: Takashi Hirao ,  Mamoru Furuta ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu

Inventor： Takashi Hirao ,  Mamoru Furuta ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu

IPC: H01L21/00

CPC classification number: H01L21/02422 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02554 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78693

Abstract: A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.

Abstract translation: 半导体器件包括氧化物半导体薄膜层，其主要包括具有除（002）取向之外的至少一个取向的氧化锌。 氧化锌可以具有包括（002）取向和（101）取向的混合取向。 或者，氧化锌可以具有包括（100）取向和（101）取向的混合取向。

公开(公告)号：US20090286351A1

公开(公告)日：2009-11-19

申请号：US12509852

申请日：2009-07-27

Applicant: Takashi HIRAO ,  Takahiro HIRAMATSU ,  Mamoru FURUTA ,  Hiroshi FURUTA ,  Tokiyoshi MATSUDA

Inventor： Takashi HIRAO ,  Takahiro HIRAMATSU ,  Mamoru FURUTA ,  Hiroshi FURUTA ,  Tokiyoshi MATSUDA

IPC: H01L21/34

CPC classification number: H01L29/7869 ,  H01L29/04 ,  H01L29/045 ,  H01L29/78618

Abstract: A manufacturing method of a semiconductor device includes forming an oxide semiconductor thin film layer of zinc oxide, wherein at least a portion of the oxide semiconductor thin film layer in an as-deposited state includes lattice planes having a preferred orientation along a direction perpendicular to the substrate and a lattice spacing d002 of at least 2.619 Å.

Abstract translation: 半导体器件的制造方法包括形成氧化锌的氧化物半导体薄膜层，其中以沉积状态的氧化物半导体薄膜层的至少一部分包括沿着垂直于所述氧化物半导体层的方向具有优选取向的晶格面 衬底和至少2.619埃的晶格间距d002。

公开(公告)号：US5397718A

公开(公告)日：1995-03-14

申请号：US19682

申请日：1993-02-19

Applicant: Mamoru Furuta ,  Tetsuya Kawamura ,  Tatsuo Yoshioka ,  Hiroshi Sano ,  Yutaka Miyata

Inventor： Mamoru Furuta ,  Tetsuya Kawamura ,  Tatsuo Yoshioka ,  Hiroshi Sano ,  Yutaka Miyata

IPC: H01L21/3215 ,  H01L21/336 ,  H01L29/786 ,  H01L21/265

CPC classification number: H01L29/66757 ,  H01L21/32155 ,  H01L29/66765 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S148/15

Abstract: In a method of manufacturing a thin film transistor, when impurity ions are introduced in a channel region between source and drain regions in a semiconductor layer, an insulator layer is first formed on the semiconductor layer. Then, impurity ions generated on high frequency discharge are introduced through the insulator layer into the semiconductor layer under a specified acceleration voltage. Then, the introduction depth of impurities and the amount of the impurities to be introduced in the channel region can be controlled or the threshold voltage of the thin film transistor can be controlled. This method can be applied to a large substrate.

Abstract translation: 在制造薄膜晶体管的方法中，当在半导体层中的杂质离子被引入源极和漏极区域之间的沟道区域中时，首先在半导体层上形成绝缘体层。 然后，在规定的加速电压下，在高频放电中产生的杂质离子通过绝缘体层导入半导体层。 然后，可以控制杂质的引入深度和引入沟道区域中的杂质的量，或者可以控制薄膜晶体管的阈值电压。 该方法可以应用于大型基板。

公开(公告)号：US5351145A

公开(公告)日：1994-09-27

申请号：US818573

申请日：1992-01-09

Applicant: Yutaka Miyata ,  Mamoru Furuta ,  Tatsuo Yoshioka ,  Hiroshi Tsutsu ,  Tetsuya Kawamura

Inventor： Yutaka Miyata ,  Mamoru Furuta ,  Tatsuo Yoshioka ,  Hiroshi Tsutsu ,  Tetsuya Kawamura

IPC: G02F1/133 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/36 ,  G11C11/00 ,  G11C11/404

CPC classification number: G11C11/404 ,  G09G3/3648 ,  G09G3/3659 ,  G09G3/3677 ,  G11C11/005 ,  G02F2001/136245 ,  G09G2300/0823 ,  G09G2320/0204 ,  G09G2320/0219

Abstract: An active matrix substrate includes a transparent substrate, pairs each having an n-type thin-film transistor and a p-type thin-film transistor formed on the transparent substrate, gate bus lines and source bus lines connected to the n-type and p-type transistors for controlling the n-type and p-type transistors, and pixel-corresponding electrodes controlled by the transistor pairs respectively. Drains of an n-type transistor and a p-type transistor in each of the pairs are connected to each other via a related pixel corresponding electrode. First pulses are applied to gates of the n-type transistors. Second pulses are applied to gates of the p-type transistors. There is provided a difference in phase between the first pulses and the second pulses.

Abstract translation: 有源矩阵基板包括透明基板，每个具有n型薄膜晶体管的对和形成在透明基板上的p型薄膜晶体管，栅极总线和连接到n型和p型的源极总线 用于控制n型和p型晶体管的晶体管，以及由晶体管对控制的像素对应的电极。 每对中的n型晶体管和p型晶体管的漏极通过相关的像素对应电极彼此连接。 第一脉冲施加到n型晶体管的栅极。 第二脉冲施加到p型晶体管的栅极。 提供了第一脉冲和第二脉冲之间的相位差。

公开(公告)号：US07981734B2

公开(公告)日：2011-07-19

申请号：US12499559

申请日：2009-07-08

Applicant: Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

Inventor： Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

IPC: H01L21/302

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618

Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.

Abstract translation: 薄膜晶体管的制造方法包括在基板上形成一对源极/漏极，使得源极/漏极在其间限定间隙; 在源/漏电极上形成限定它们之间的间隙的低电阻导电薄膜; 以及在低电阻导电薄膜的上表面和限定在低电阻导电薄膜之间的间隙中形成氧化物半导体薄膜层，使得氧化物半导体薄膜层用作沟道。 蚀刻低电阻导电薄膜和氧化物半导体薄膜层，使得电阻导电薄膜的侧表面和氧化物半导体薄膜层的相应侧表面在沟道的沟道宽度方向上彼此重合。 栅电极安装在氧化物半导体薄膜层上。