公开(公告)号：US20060118958A1

公开(公告)日：2006-06-08

申请号：US11281837

申请日：2005-11-17

Applicant: Hyang-Ja Yang ,  Kang-Young Kim

Inventor： Hyang-Ja Yang ,  Kang-Young Kim

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L27/1104 ,  H01L27/11 ,  Y10S257/903 ,  Y10S257/909

Abstract: A line layout structure comprises first metal lines disposed in a first direction on a cell array region to form first power lines for supplying power to static memory cells, second metal lines disposed over the first metal lines in a second direction substantially perpendicular to the first metal lines to form second power lines for supplying power to the first power lines, third metal lines disposed over the second metal lines to form third power lines for supplying power to the second power lines, and fourth metal lines disposed over the third metal lines to form fourth power lines for supplying power to the third power lines.

Abstract translation: 线路布置结构包括在单元阵列区域上沿第一方向布置的第一金属线，以形成用于向静态存储单元供电的第一电力线，第二金属线沿着基本垂直于第一金属的第二方向设置在第一金属线上 线形成用于向第一电力线供电的第二电力线，设置在第二金属线上的第三金属线，以形成用于向第二电力线供电的第三电力线，以及设置在第三金属线上的第四金属线，以形成 用于向第三电力线供电的第四电力线。

公开(公告)号：US07436078B2

公开(公告)日：2008-10-14

申请号：US11281837

申请日：2005-11-17

Applicant: Hyang-Ja Yang ,  Kang-Young Kim

Inventor： Hyang-Ja Yang ,  Kang-Young Kim

IPC: H01L23/58

CPC classification number: H01L27/1104 ,  H01L27/11 ,  Y10S257/903 ,  Y10S257/909

Abstract: An apparatus including a trolling motor having at least one operational subsystem and the trolling motor also having an integral electronic controller for controlling the operational subsystem wherein the improvement comprises an integral electronic diagnostic system which will receive diagnostic information from the operational subsystem and will transmit the diagnostic information for reception externally of the trolling motor.

Abstract translation: 一种包括具有至少一个操作子系统的拖钓马达的装置，并且拖钓马达还具有用于控制操作子系统的整体式电子控​​制器，其中改进包括一体式电子诊断系统，该系统将从操作子系统接收诊断信息，并将传送诊断 用于在拖钓电机外部接收的信息。

公开(公告)号：US6088277A

公开(公告)日：2000-07-11

申请号：US340556

申请日：1999-06-28

Applicant: Kang-Young Kim ,  Byeng-Sun Choi

Inventor： Kang-Young Kim ,  Byeng-Sun Choi

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C17/06 ,  G11C17/12 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C17/126 ,  G11C7/065 ,  G11C7/1006

Abstract: A read-only memory device having a NOR structure is provided. The memory device comprises a memory cell array having a plurality of memory cells, each memory cell storing data, a plurality of first bit lines coupled to the array, and a plurality of second bit lines coupled to the array. A first selection circuit are coupled to the plurality of first bit lines for selecting at least two adjacent first bit lines. A second selection circuit coupled to the plurality of second bit lines for selecting at least two adjacent second bit lines. A sense amplification circuit detect a cell state of a selected memory cell by biasing the selected first bit lines and one of the selected second bit lines with a same potential. The second selection circuit grounds another of the selected second bit lines. The first selection circuit grounds unselected first bit lines and wherein the second selection circuit grounds unselected second bit lines. According to the mask ROM of the present invention, leakage current paths to the biased main and ground bit lines are cut off during a data reading operation of an off-cell. The biased main and ground bit lines can be charged by only one sense amplification circuit.

Abstract translation: 提供具有NOR结构的只读存储器件。 存储器件包括具有多个存储器单元的存储单元阵列，每个存储单元存储数据，耦合到阵列的多个第一位线以及耦合到阵列的多个第二位线。 第一选择电路耦合到多个第一位线，用于选择至少两个相邻的第一位线。 耦合到所述多个第二位线的第二选择电路，用于选择至少两个相邻的第二位线。 感测放大电路通过偏置所选择的第一位线和所选择的第二位线之一以相同的电位来检测所选存储单元的单元状态。 第二选择电路接地另一个选定的第二位线。 第一选择电路接地未选择的第一位线，并且其中第二选择电路接地未选择的第二位线。 根据本发明的掩模ROM，在离电池的数据读取操作期间，切断偏置的主位线和接地位线的漏电流路径。 偏置的主位线和地线位线只能由一个读出放大电路充电。

公开(公告)号：US20070181148A1

公开(公告)日：2007-08-09

申请号：US11642893

申请日：2006-12-21

Applicant: Min-Sang Yun ,  Kwon Son ,  Jae-Hyung Jung ,  Hee-Chan Jung ,  Ki-Ryong Choi ,  Byung-Joo Park ,  Kang-Young Kim

Inventor： Min-Sang Yun ,  Kwon Son ,  Jae-Hyung Jung ,  Hee-Chan Jung ,  Ki-Ryong Choi ,  Byung-Joo Park ,  Kang-Young Kim

IPC: C23G1/00 ,  B08B3/00 ,  B08B7/00

CPC classification number: H01L21/67051 ,  H01L21/02052

Abstract: Embodiments of the invention provide a semiconductor wafer cleaning apparatus and a related method. In one embodiment, the invention provides a semiconductor wafer cleaning apparatus comprising a wafer stage adapted to support a wafer; a first cleaning unit adapted to spray a first cleaning solution onto the wafer to remove particles from the wafer, wherein the first cleaning solution prevents static electricity from being generated on the surface of the wafer; and a second cleaning unit adapted to provide a second cleaning solution onto the wafer and oscillate a quartz rod to remove particles from the wafer, wherein the second cleaning solution makes a surface of the wafer hydrophilic.

Abstract translation: 本发明的实施例提供一种半导体晶片清洗装置及相关方法。 在一个实施例中，本发明提供一种半导体晶片清洁设备，其包括适于支撑晶片的晶片台; 第一清洁单元，其适于将第一清洁溶液喷射到所述晶片上以从所述晶片去除颗粒，其中所述第一清洁溶液防止在所述晶片的表面上产生静电; 以及第二清洁单元，其适于将第二清洁溶液提供到所述晶片上并振荡石英棒以从所述晶片去除颗粒，其中所述第二清洁溶液使所述晶片的表面具有亲水性。