公开(公告)号：US09812752B2

公开(公告)日：2017-11-07

申请号：US15218626

申请日：2016-07-25

Applicant: QUALCOMM Incorporated

Inventor： John Jong-Hoon Lee ,  Young Kyu Song ,  Uei-Ming Jow ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01P1/20 ,  H01P7/06 ,  H01L21/00 ,  H01L27/15 ,  H01L23/66 ,  H01L49/02 ,  H03B5/18 ,  H01P1/201 ,  H01P1/207 ,  H01L23/552 ,  H01L21/48 ,  H01L23/522 ,  H01L23/60 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01P1/207 ,  H01L21/4853 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L24/16 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6627 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2224/10 ,  H01L2224/16227 ,  H01P1/201 ,  H01P7/06 ,  H01P7/065 ,  H03B5/1817 ,  H05K1/0243

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

公开(公告)号：US09613831B2

公开(公告)日：2017-04-04

申请号：US14959129

申请日：2015-12-04

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L21/50 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/373

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/56 ,  H01L2221/68304 ,  H01L21/304 ,  H01L21/30604 ,  H01L2221/68381

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

公开(公告)号：US20170025343A1

公开(公告)日：2017-01-26

申请号：US15284514

申请日：2016-10-03

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract translation: 电路基板具有以下元件。 层叠电路结构具有与其相对的第一表面和第二表面。 第一图案化内导电层设置在第一表面上并具有多个焊盘。 第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。 第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。 应用上述电路基板的半导体封装结构及其制造方法也在这里提供。

公开(公告)号：US09497864B2

公开(公告)日：2016-11-15

申请号：US13898486

申请日：2013-05-21

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H01L23/13 ,  H01L23/367 ,  H01L23/498 ,  H05K3/28

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract translation: 电路基板具有以下元件。 层叠电路结构具有与其相对的第一表面和第二表面。 第一图案化内导电层设置在第一表面上并具有多个焊盘。 第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。 第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。 应用上述电路基板的半导体封装结构及其制造方法也在这里提供。

公开(公告)号：US09349628B2

公开(公告)日：2016-05-24

申请号：US13848549

申请日：2013-03-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei-Chin Lau ,  Hai-Wah Lim

IPC: H05K3/00 ,  H01L21/68 ,  H01L23/16 ,  H01L23/00 ,  H05K3/34

CPC classification number: H01L21/68 ,  H01L23/16 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/10 ,  H01L2224/10155 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/0008 ,  H05K3/3436 ,  H05K2201/09145 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0165 ,  H05K2203/0169 ,  H05K2203/0278 ,  H05K2203/167 ,  Y10T29/49124 ,  Y10T29/49133 ,  Y10T29/53178 ,  Y10T156/10 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods and apparatus for coupling a stiffener frame to a circuit board are disclosed. In one aspect, a method for engaging a stiffener frame and a circuit board positioned in a fixture is provided. The method includes positioning an alignment plate on the stiffener frame, such that a downwardly facing shoulder of a bottom opening of the alignment plate is seated on a setback of the stiffener frame, wherein the bottom opening of the alignment plate is larger than the a top opening of the alignment plate. The circuit board is positioned on the stiffener frame. The alignment plate restrains movement of the circuit board relative to the stiffener frame with a peripheral wall of a the top opening of the alignment plate.

Abstract translation: 公开了用于将加强框架耦合到电路板的方法和装置。 一方面，提供了一种用于接合加强框架和定位在固定装置中的电路板的方法。 该方法包括将对准板定位在加强框架上，使得对准板的底部开口的向下的肩部位于加强框架的挫折上，其中对准板的底部开口大于顶部 对准板的开口。 电路板位于加强框架上。 对准板限制了电路板相对于加强框架的移动，同时具有对准板的顶部开口的周壁。

公开(公告)号：US09293403B2

公开(公告)日：2016-03-22

申请号：US13955422

申请日：2013-07-31

Applicant: Amkor Technology, Inc.

Inventor： No Sun Park ,  Ji Yeon Ryu ,  Go Woon Jung

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/05078 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06137 ,  H01L2224/10 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled to a solder bump via under bump metal layers. A second RDL is formed in a same plane of the semiconductor die as the first RDL and is electrically isolated from the first RDL. A first end of the second RDL may be coupled to a bond pad and the second RDL may pass underneath, but be electrically isolated from, the solder bump. A passivation layer may be formed on the first and second RDLs exposing the second end of the first RDL. The under bump metal layers may be formed on the second end of the first RDL exposed by the passivation layer.

Abstract translation: 公开了具有改进的再分布层设计及其制造方法的半导体封装，并且可以包括半导体管芯，其包括接合焊盘，形成在半导体管芯上的第一再分配层（RDL）。 第一RDL具有耦合到接合焊盘的第一端和通过下凸块金属层耦合到焊料凸块的第二端。 第二RDL形成在与第一RDL相同的半导体管芯的平面中，并且与第一RDL电隔离。 第二RDL的第一端可以耦合到接合焊盘，并且第二RDL可以在下面通过，但是与焊料凸块电隔离。 可以在露出第一RDL的第二端的第一和第二RDL上形成钝化层。 底部凸块金属层可以形成在由钝化层暴露的第一RDL的第二端上。

公开(公告)号：US09253880B2

公开(公告)日：2016-02-02

申请号：US13689031

申请日：2012-11-29

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Mi Jin Park ,  Romero Christian ,  Seung Wook Park

IPC: H05K1/03 ,  H05K1/02 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L2224/10 ,  H05K1/0237 ,  H05K3/4038 ,  H05K3/4644 ,  H05K2201/09681 ,  H05K2201/09972 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed herein is a printed circuit board, including: a core layer; and a plurality of circuit layers stacked on the core layer, wherein one of the circuit layers includes a mesh pattern and a solid pattern, and another of the circuit layers include a first signal pattern opposite to the mesh pattern and a second signal pattern opposite to the solid pattern, the second signal pattern having a high-speed signal line with a higher speed, as compared with the second signal pattern.

Abstract translation: 这里公开了一种印刷电路板，包括：芯层; 以及堆叠在所述芯层上的多个电路层，其中所述电路层中的一个包括网格图案和固体图案，并且所述电路层中的另一个包括与所述网格图案相对的第一信号图案和与所述网格图案相对的第二信号图案 固体图案，第二信号图案具有与第二信号图案相比具有较高速度的高速信号线。

公开(公告)号：US09219091B2

公开(公告)日：2015-12-22

申请号：US14200158

申请日：2014-03-07

Applicant: Optiz, Inc.

Inventor： Vage Oganesian ,  Zhenhua Lu

IPC: H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/14618 ,  H01L27/14685 ,  H01L2224/10

Abstract: A host substrate assembly includes a first substrate with opposing first and second surfaces, an aperture extending therethrough, circuit layers, and first contact pads electrically coupled to the circuit layers. A sensor chip includes a second substrate with opposing first and second surfaces, a plurality of photo detectors formed on or in the second substrate and configured to receive light incident on the second substrate first surface, and a plurality of second contact pads formed at the second substrate first or second surfaces and are electrically coupled to the photo detectors. A spacer is mounted to the second substrate first surface. A protective substrate is mounted to the spacer and disposed over the photo detectors. Electrically conductive conduits each extend through the spacer and are in electrical contact with one of the second contact pads. Electrical connectors electrically connect the first contact pads and the conduits.

Abstract translation: 主机基板组件包括具有相对的第一和第二表面的第一基板，延伸穿过其中的孔，电路层和电耦合到电路层的第一接触焊盘。 传感器芯片包括具有相对的第一和第二表面的第二基板，形成在第二基板上或第二基板中并被配置为接收入射在第二基板第一表面上的光的多个光电检测器，以及形成在第二基板上的多个第二接触焊盘 基板第一或第二表面，并且电耦合到光电检测器。 间隔件安装到第二基板第一表面。 保护衬底被安装到间隔件并设置在光电检测器上。 导电导管各自延伸穿过间隔件并与第二接触垫中的一个电接触。 电连接器电连接第一接触垫和导管。

公开(公告)号：US20130277829A1

公开(公告)日：2013-10-24

申请号：US13452636

申请日：2012-04-20

Applicant: Kuo-Chung Yee ,  Chun Hui Yu

Inventor： Kuo-Chung Yee ,  Chun Hui Yu

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/10 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/10 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.

Abstract translation: 一种制造三维集成电路的方法包括在包装部件的第一侧上形成再分配层，在再分布层中形成保持室，将集成电路管芯附接在包装部件的第一侧上，其中互连凸块 的集成电路管芯插入到保持室中，对集成电路管芯和封装部件进行回流处理，并在封装部件上形成封装层。

公开(公告)号：US20130256895A1

公开(公告)日：2013-10-03

申请号：US13436124

申请日：2012-03-30

Applicant: Michael Su ,  Bryan Black ,  Joe Siegel ,  Neil McLellan ,  Michael Alfano

Inventor： Michael Su ,  Bryan Black ,  Joe Siegel ,  Neil McLellan ,  Michael Alfano

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/10 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14136 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/29076 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of manufacturing is provided that includes fabricating a first set of interconnect structures on a side of a first semiconductor substrate. The first semiconductor substrate is operable to have at least one of plural semiconductor substrates stacked on the side. The first set of interconnect structures is arranged in a pattern. Each of the plural semiconductor substrates has a second set of interconnect structures arranged in the pattern, one of the plural semiconductor substrates has a smallest footprint of the plural semiconductor substrates. The pattern has a footprint smaller than the smallest footprint of the plural semiconductor substrates.

Abstract translation: 提供一种制造方法，其包括在第一半导体衬底的侧面上制造第一组互连结构。 第一半导体衬底可操作以具有堆叠在一侧的多个半导体衬底中的至少一个。 第一组互连结构以图案布置。 多个半导体衬底中的每一个具有以图案布置的第二组互连结构，多个半导体衬底中的一个半导体衬底的占用面积最小。 该图案的占地面积小于多个半导体衬底的最小占地面积。