Invention Application
- Patent Title: Method of Fabricating Three Dimensional Integrated Circuit
- Patent Title (中): 制造三维集成电路的方法
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Application No.: US13452636Application Date: 2012-04-20
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Publication No.: US20130277829A1Publication Date: 2013-10-24
- Inventor: Kuo-Chung Yee , Chun Hui Yu
- Applicant: Kuo-Chung Yee , Chun Hui Yu
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/56

Abstract:
A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.
Public/Granted literature
- US08741691B2 Method of fabricating three dimensional integrated circuit Public/Granted day:2014-06-03
Information query
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