Invention Application
US20130277829A1 Method of Fabricating Three Dimensional Integrated Circuit 有权
制造三维集成电路的方法

Method of Fabricating Three Dimensional Integrated Circuit
Abstract:
A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.
Public/Granted literature
Information query
Patent Agency Ranking
0/0