公开(公告)号：US20140217567A1

公开(公告)日：2014-08-07

申请号：US14157714

申请日：2014-01-17

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Koichi Nakamura

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L21/563 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8113 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/831 ,  H01L2224/83385 ,  H01L2224/83447 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/85447 ,  H01L2224/92 ,  H01L2224/92163 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2924/014 ,  H01L21/304 ,  H01L21/78 ,  H01L2224/83 ,  H01L2224/85 ,  H01L21/56 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor chip, a protruding pillar electrode provided on the semiconductor chip, and resin covering the semiconductor chip and the pillar electrode. The resin has a concave part and exposes a front edge portion of the pillar electrode from the resin at the bottom face of the concave part. The front edge portion of the pillar electrode is exposed from the concave part of the resin, which makes it possible to suppress increase in the height of the pillar electrode and to form the pillar electrodes having fine patterns or a narrow pitch.

摘要翻译： 半导体封装包括半导体芯片，设置在半导体芯片上的突出的柱状电极以及覆盖半导体芯片和柱状电极的树脂。 树脂具有凹部，并且从凹部的底面的树脂露出柱状电极的前端部。 柱状电极的前端部从树脂的凹部露出，能够抑制柱状电极的高度的增加，并形成具有精细图案或窄间距的柱状电极。

公开(公告)号：US08794502B2

公开(公告)日：2014-08-05

申请号：US13760350

申请日：2013-02-06

申请人： Electronics and Telecommuniations Research Institute

发明人： Yong Sung Eom ,  Kwang-Seong Choi ,  Jung Hyun Noh

IPC分类号： B23K31/02 ,  H01L21/44

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/11442 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/13601 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29301 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/83192 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01029

摘要： Disclosed are a method of forming a solder on pad on a fine pitch PCB and a method of flip chip bonding a semiconductor device using the same. The method of forming a solder on pad on a fine pitch PCB includes: applying a solder bump maker (SBM) paste with a predetermined thickness to an entire surface of a PCB including a metal pad and a solder mask; heating the SBM paste at a temperature higher than a melting point of solder contained in the SBM paste and then cooling the SBM paste to form a solder on pad; and washing a residual polymer resin and residual solder particles of the SBM paste by using a solvent.

摘要翻译： 公开了一种在精细间距PCB上焊盘上形成焊料的方法以及使用该焊料的半导体器件的倒装芯片接合方法。 在精细间距PCB上的焊盘上形成焊料的方法包括：将具有预定厚度的焊料凸块制造商（SBM）浆料施加到包括金属焊盘和焊接掩模的PCB的整个表面; 在高于SBM糊料中所含焊料熔点的温度下加热SBM糊料，然后冷却SBM糊料以在焊盘上形成焊料; 并使用溶剂洗涤残留的聚合物树脂和SBM糊的残留焊料颗粒。

公开(公告)号：US20130334291A1

公开(公告)日：2013-12-19

申请号：US13760350

申请日：2013-02-06

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Yong Sung EOM ,  Kwang-Seong Choi ,  Jung Hyun Noh

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/11442 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/13601 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29301 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/83192 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01029

摘要： Disclosed are a method of forming a solder on pad on a fine pitch PCB and a method of flip chip bonding a semiconductor device using the same. The method of forming a solder on pad on a fine pitch PCB includes: applying a solder bump maker (SBM) paste with a predetermined thickness to an entire surface of a PCB including a metal pad and a solder mask; heating the SBM paste at a temperature higher than a melting point of solder contained in the SBM paste and then cooling the SBM paste to form a solder on pad; and washing a residual polymer resin and residual solder particles of the SBM paste by using a solvent.

摘要翻译： 公开了一种在精细间距PCB上焊盘上形成焊料的方法以及使用该焊料的半导体器件的倒装芯片接合方法。 在精细间距PCB上的焊盘上形成焊料的方法包括：将具有预定厚度的焊料凸块制造商（SBM）浆料施加到包括金属焊盘和焊接掩模的PCB的整个表面; 在高于SBM糊料中所含焊料熔点的温度下加热SBM糊料，然后冷却SBM糊料以在焊盘上形成焊料; 并使用溶剂洗涤残留的聚合物树脂和SBM糊的残留焊料颗粒。

公开(公告)号：US20130207258A1

公开(公告)日：2013-08-15

申请号：US13370895

申请日：2012-02-10

申请人： Hsien-Wei CHEN ,  Yi-Wen WU

发明人： Hsien-Wei CHEN ,  Yi-Wen WU

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.

摘要翻译： 一种半导体器件，包括形成在钝化后互连（PPI）结构的表面上的电介质层。 在电介质层上形成聚合物层并用开口图案化以暴露电介质层的一部分。 然后去除介电层的暴露部分以暴露PPI结构的一部分。 然后在PPI结构的第一部分上方形成焊料凸块并与其电连接。

公开(公告)号：US20130113115A1

公开(公告)日：2013-05-09

申请号：US13290208

申请日：2011-11-07

申请人： Tsung-Ding Wang ,  Chien-Hsiun Lee

发明人： Tsung-Ding Wang ,  Chien-Hsiun Lee

IPC分类号： H01L23/52 ,  H01L21/50

CPC分类号： H01L23/145 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/074 ,  H01L25/112 ,  H01L25/115 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/14132 ,  H01L2224/14165 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K3/403

摘要： A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

摘要翻译： 一种方法包括将具有多个集成电路（IC）管芯的衬底连接到封装衬底，使得封装衬底延伸超过衬底的至少两个边缘，留下封装衬底的第一和第二边缘部分具有暴露的触点。 第一和第二边缘部分在封装基板的第一角处相交。 至少第一上模封装被放置在衬底上，使得第一上模封装的第一和第二边缘部分延伸超过衬底的至少两个边缘。 第一上模组件的第一和第二边缘部分上的垫连接到封装衬底的第一和第二边缘部分的触头。

公开(公告)号：US08404522B2

公开(公告)日：2013-03-26

申请号：US13172945

申请日：2011-06-30

申请人： Goji Shiga ,  Naohide Takamoto ,  Fumiteru Asai

发明人： Goji Shiga ,  Naohide Takamoto ,  Fumiteru Asai

IPC分类号： H01L21/00

CPC分类号： H01L21/6836 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68386 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  Y10T428/24959 ,  Y10T428/265 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/00

摘要： The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 μm to 40 μm.

摘要翻译： 本发明涉及一种半导体背面用切割带一体化膜，其特征在于，具有：依次层叠有基材和粘合剂层的切割带和设置在所述压敏粘合剂上的半导体背面用膜 切割胶带的层，其中压敏粘合剂层的厚度为20μm至40μm。

公开(公告)号：US20130000963A1

公开(公告)日：2013-01-03

申请号：US13616217

申请日：2012-09-14

申请人： Charles Gerard Woychick ,  John Eric Tkaczyk ,  Brian David Yanoff ,  Tan Zhang

发明人： Charles Gerard Woychick ,  John Eric Tkaczyk ,  Brian David Yanoff ,  Tan Zhang

IPC分类号： H05K1/09 ,  H05K1/00

CPC分类号： H01L24/16 ,  H01L21/563 ,  H01L22/20 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1411 ,  H01L2224/1601 ,  H01L2224/16106 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/81011 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81194 ,  H01L2224/812 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/8191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/351 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49179 ,  H01L2924/05432 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2224/05552

摘要： A micro pin hybrid interconnect array includes a crystal anode array and a ceramic substrate. The array and substrate are joined together using an interconnect geometry having a large aspect ratio of height to width. The joint affixing the interconnect to the crystal anode array is devoid of solder.

摘要翻译： 微针混合互连阵列包括晶体阳极阵列和陶瓷衬底。 使用具有高宽比大的纵横比的互连几何形状将阵列和衬底连接在一起。 将互连连接到晶体阳极阵列的接头没有焊料。

公开(公告)号：US08247270B2

公开(公告)日：2012-08-21

申请号：US12990220

申请日：2009-05-13

申请人： Hiroki Nikaido ,  Mitsuo Sugino

发明人： Hiroki Nikaido ,  Mitsuo Sugino

IPC分类号： H01L21/44

CPC分类号： H01L23/49816 ,  C09J163/00 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3114 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/94 ,  H01L2221/68336 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/27416 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29388 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/8191 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1579 ,  H05K3/0052 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/0503 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A method of manufacturing a semiconductor component of the present invention has: obtaining a semiconductor wafer having stud electrodes formed on a functional surface thereof, and a circuit board having solder bumps on one surface and having electrode pads on the other surface thereof; bonding the semiconductor wafer and the circuit board, while providing a resin layer having a flux activity between the semiconductor wafer and the circuit board, and so as to bring the stud electrodes into contact with the solder bumps, while penetrating the resin layer having a flux activity, to thereby obtain a bonded structure; applying a solder material onto the electrode pads of the bonded structure; and dicing the bonded structure to obtain a plurality of semiconductor components.

摘要翻译： 本发明的半导体部件的制造方法具有：获得具有形成在其功能面上的双面电极的半导体晶片和在一个表面上具有焊料凸块的电路板，并在其另一个表面上具有电极焊盘; 接合半导体晶片和电路板，同时提供在半导体晶片和电路板之间具有通量活性的树脂层，并且使得柱状电极与焊料凸块接触，同时穿透具有焊剂的树脂层 活性，从而获得结合结构; 在焊接结构的电极焊盘上施加焊料; 并且对结合结构进行切割以获得多个半导体部件。

公开(公告)号：US20120028415A1

公开(公告)日：2012-02-02

申请号：US13172945

申请日：2011-06-30

申请人： Goji SHIGA ,  Naohide TAKAMOTO ,  Fumiteru ASAI

发明人： Goji SHIGA ,  Naohide TAKAMOTO ,  Fumiteru ASAI

IPC分类号： H01L21/78 ,  B32B7/02 ,  B32B3/00

CPC分类号： H01L21/6836 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68386 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/92125 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  Y10T428/24959 ,  Y10T428/265 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/00

摘要： The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 μm to 40 μm.

摘要翻译： 本发明涉及一种半导体背面用切割带一体化膜，其特征在于，具有：依次层叠有基材和粘合剂层的切割带和设置在所述压敏粘合剂上的半导体背面用膜 切割胶带的层，其中压敏粘合剂层的厚度为20μm至40μm。

公开(公告)号：US20120024469A1

公开(公告)日：2012-02-02

申请号：US13170581

申请日：2011-06-28

申请人： Naohide TAKAMOTO ,  Goji SHIGA ,  Fumiteru ASAI

发明人： Naohide TAKAMOTO ,  Goji SHIGA ,  Fumiteru ASAI

IPC分类号： H01L21/02 ,  B32B38/04 ,  B32B38/10 ,  B65D65/28

CPC分类号： H01L21/6836 ,  B32B37/1284 ,  B32B38/0004 ,  B32B38/10 ,  B32B2405/00 ,  B32B2457/14 ,  C09J7/20 ,  C09J165/00 ,  C09J2201/606 ,  C09J2203/326 ,  C09J2461/00 ,  C09J2463/00 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3164 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/5448 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29386 ,  H01L2224/73204 ,  H01L2224/81095 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  Y10T156/1052 ,  Y10T156/1064 ,  Y10T156/1075 ,  Y10T156/1077 ,  Y10T156/1082 ,  Y10T156/1093 ,  Y10T428/1471 ,  Y10T428/1476 ,  Y10T428/1495 ,  Y10T428/15 ,  Y10T428/21 ,  H01L21/78 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2224/13099

摘要： The present invention relates to a film for semiconductor device production, which includes: a separator; and a plurality of adhesive layer-attached dicing tapes each including a dicing tape and an adhesive layer laminated on the dicing tape, which are laminated on the separator at a predetermined interval in such a manner that the adhesive layer attaches to the separator, in which the separator has a cut formed along the outer periphery of the dicing tape, and the depth of the cut is at most ⅔ of the thickness of the separator.

摘要翻译： 本发明涉及一种用于半导体器件生产的膜，其包括：隔板; 以及多个粘附层附着的切割带，每个粘合剂层附着的切割带包括层合在切割带上的切割带和粘合剂层，它们以预定的间隔层压在隔板上，使得粘合剂层附着到隔板上，其中 分离器具有沿着切割带的外周形成的切口，并且切割深度为隔板的厚度的至多。。