公开(公告)号：US20240339489A1

公开(公告)日：2024-10-10

申请号：US18745970

申请日：2024-06-17

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： Joo Woan CHO ,  Dae Ho SONG ,  Tae Hee LEE ,  Hyung Il JEON ,  Byeong Hwa CHOI

IPC分类号： H01L27/15 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H01L27/105

CPC分类号： H01L27/156 ,  H01L23/481 ,  H01L24/06 ,  H01L25/18 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L27/105 ,  H01L2224/05025 ,  H01L2224/05541 ,  H01L2224/0613 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/48229

摘要： A display device includes a first substrate including a display area, a non-display area, and a plurality of pixel circuit units in the display area and the non-display area, a plurality of light emitting elements on the first substrate in the display area, the plurality of light emitting elements being electrically connected to the pixel circuit units, a hole mask layer on the first substrate and including a plurality of holes corresponding to the light emitting elements, a second substrate on the hole mask layer and including a plurality of open holes corresponding to the plurality of holes, and a plurality of light exit patterns in the plurality of the open holes of the second substrate corresponding to the plurality of holes, wherein each of the light exit patterns includes a first part in one of the plurality of open holes.

公开(公告)号：US20240222303A1

公开(公告)日：2024-07-04

申请号：US18226589

申请日：2023-07-26

申请人： Samsung Electronics Co., Ltd.

发明人： Daehyun KIM ,  KUNSIL LEE

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0613 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1413 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815

摘要： Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.

公开(公告)号：US20230299123A1

公开(公告)日：2023-09-21

申请号：US17698939

申请日：2022-03-18

申请人： Intel Corporation

发明人： Qiang Yu ,  Gwang-Soo Kim ,  Said Rami

IPC分类号： H01L49/02 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L28/10 ,  H01L24/08 ,  H01L23/5227 ,  H01L24/06 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/06051 ,  H01L2224/0603 ,  H01L2224/0615 ,  H01L2224/0613 ,  H01L25/0652

摘要： In one embodiment, an apparatus includes a first integrated circuit die with metal bonding pads that are co-planar with an external surface of the die and a second integrated circuit die with metal bonding pads that are co-planar with an external surface of the die. The first and second integrated circuit dies are coupled together such that their external surfaces are in contact and the metal pads of the first integrated circuit die are in direct contact with respective metal pads of the second integrated circuit die. The apparatus also includes an inductor formed at least partially by the metal pads of the first integrated circuit die and the metal pads of the second integrated circuit die.

公开(公告)号：US20230187372A1

公开(公告)日：2023-06-15

申请号：US17886333

申请日：2022-08-11

申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

发明人： Tsung-Yi HUNG ,  Yu-Wei HUANG

IPC分类号： H01L23/544 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/544 ,  H01L24/20 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/1413 ,  H01L24/14 ,  H01L2224/2105 ,  H01L2224/2205 ,  H01L2223/54426 ,  H01L2224/05555 ,  H01L2224/0613

摘要： An electronic device includes a via-array substrate, an outer layer, and an alignment substrate. The via-array substrate has a plurality of first vias. The outer layer has a plurality of second vias and is disposed on a side of the via-array substrate. The first vias are greater in distribution density or quantity than the second vias. A part of the first vias is electrically connected to the second vias, and another part of the first vias is electrically floating. The alignment substrate includes a core layer disposed on the outer layer, a plurality of conductive traces, a plurality of interconnecting pads, and a plurality of alignment mark pads. The conductive traces are disposed in the core layer. The interconnecting pads and the alignment mark pads are disposed on a surface of the core layer located away from the outer layer. A part of the conductive traces electrically connects a part of the interconnecting pads and a part of the first vias. A pattern of each of the alignment mark pads is different from a pattern of each of the interconnecting pads.

公开(公告)号：US20230154879A1

公开(公告)日：2023-05-18

申请号：US17717674

申请日：2022-04-11

申请人： SK hynix Inc.

发明人： Si Yun KIM ,  Kang Hun KIM ,  Jun Yong SONG

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/05 ,  H01L24/13 ,  H01L2924/3841 ,  H01L2224/1403 ,  H01L2224/1703 ,  H01L2224/16227 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13147 ,  H01L2224/14133 ,  H01L2224/0613 ,  H01L24/06 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2924/014 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/1146 ,  H01L2224/11474 ,  H01L2224/0361 ,  H01L2224/11849 ,  H01L2224/81203 ,  H01L24/81

摘要： A semiconductor device is provided. The semiconductor device includes a substrate, input and output (I/O) pads disposed at an upper portion of the semiconductor substrate, and first bump pillars disposed over the I/O pads. The first bump pillars are selectively arranged over some of the I/O pads in a first horizontal direction.

公开(公告)号：US09099318B2

公开(公告)日：2015-08-04

申请号：US13107678

申请日：2011-05-13

申请人： Hsien-Wei Chen

发明人： Hsien-Wei Chen

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/0613 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06179 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/2064 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A semiconductor chip includes a substrate, a circuit formed over the substrate, a plurality of conductive pads formed over the substrate, and a plurality of bump structures each formed over a corresponding one of the plurality of conductive pads. The plurality of conductive pads includes a first conductive pad having a first pad width and a second conductive pad having a second pad width larger than the first pad width. The first conductive pad is electrically coupled to the circuit, and the second conductive pad is positioned at a corner region of the semiconductor chip and is free from being electrically coupled to the circuit. The first conductive pad is positioned closer to a geometric center of the semiconductor chip than the second conductive pad.

摘要翻译： 半导体芯片包括衬底，在衬底上形成的电路，在衬底上形成的多个导电焊盘，以及多个凸起结构，每个凸起结构形成在多个导电焊盘中的相应一个上。 多个导电焊盘包括具有第一焊盘宽度的第一导电焊盘和具有大于第一焊盘宽度的第二焊盘宽度的第二导电焊盘。 第一导电焊盘电耦合到电路，并且第二导电焊盘位于半导体芯片的拐角区域处，并且不与电路电耦合。 第一导电焊盘定位成比第二导电焊盘更靠近半导体芯片的几何中心。

公开(公告)号：US09053943B2

公开(公告)日：2015-06-09

申请号：US13167906

申请日：2011-06-24

申请人： Yi-Mang Chou ,  Yian-Liang Kuo

发明人： Yi-Mang Chou ,  Yian-Liang Kuo

IPC分类号： H01L23/528 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05555 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/0613 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2924/00012

摘要： A bond pad design comprises a plurality of bond pads on a semiconductor chip and a plurality of under-bump metallurgy (UBM) layers formed on respective bond pads of the plurality. At least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center to the periphery of the chip.

摘要翻译： 接合焊盘设计包括半导体芯片上的多个接合焊盘和形成在多个焊盘上的多个凸点下的冶金（UBM）层。 至少一个接合焊盘具有细长形状，具有细长部分和收缩部分，细长部分基本上沿着从芯片的中心辐射到外围的应力方向取向。

公开(公告)号：US20150137125A1

公开(公告)日：2015-05-21

申请号：US14589547

申请日：2015-01-05

申请人： Renesas Electronics Corporation

发明人： Bunji Yasumura ,  Fumio Tsuchiya ,  Hisanori Ito ,  Takuji Ide ,  Naoki Kawanabe ,  Masanao Sato

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H01L2924/3512 ,  H01L2924/00

摘要： A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

摘要翻译： 提供了能够防止半导体装置的最上层的保护膜的破裂的技术，提高了半导体装置的可靠性。 在半导体芯片的主表面上形成的接合焊盘为矩形，并且在每个接合焊盘上的保护膜中形成开口，使得保护膜在每个接合的引线接合区域中的重叠宽度 衬垫比每个焊盘的探针区域中的保护膜的重叠宽度宽。

公开(公告)号：US08709913B2

公开(公告)日：2014-04-29

申请号：US13939725

申请日：2013-07-11

申请人： Tessera, Inc.

发明人： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

IPC分类号： H01L21/30

CPC分类号： H01L25/00 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/0613 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06505 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/276 ,  H01L2224/29023 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32148 ,  H01L2224/32238 ,  H01L2224/73103 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/8323 ,  H01L2224/83815 ,  H01L2224/8383 ,  H01L2224/9202 ,  H01L2224/9221 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/35 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2924/00

摘要： Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

摘要翻译： 公开了两种元件的微电子组件及其形成方法。 微电子元件包括主表面和介电层以及在主表面处暴露的至少一个接合焊盘。 微电子元件可以包含多个有源电路元件。 沉积第一金属层，覆盖至少一个接合焊盘和电介质层。 提供了具有沉积在其上的第二金属层的第二元件，并且第一金属层与第二金属层接合。 组件可以沿着切割通道切割成各自包括芯片的单元。

公开(公告)号：US08476762B2

公开(公告)日：2013-07-02

申请号：US13463879

申请日：2012-05-04

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/061 ,  H01L2224/0613 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.

摘要翻译： 用于半导体芯片封装的具有球限制冶金（BLM）结构的无铅控制崩溃芯片连接（C4）的结构和方法，其在芯片级后端（BEOL）工艺中减少芯片级开裂， 加入冷却。 在芯片连接冷却期间受到拉伸应力的BLM结构的边缘被保护以防止金属种子层的底切，由芯片的湿法蚀刻引起，以通过电镀从芯片的表面和焊料回流中去除金属层 阻挡层，其覆盖金属种子层的相应边缘。