公开(公告)号：US20230170288A1

公开(公告)日：2023-06-01

申请号：US17694445

申请日：2022-03-14

申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

发明人： Yu-Wei HUANG ,  Shau-Fei CHENG

IPC分类号： H01L23/498

CPC分类号： H01L23/49838 ,  H01L23/49816

摘要： This disclosure provides a conductive circuit carrier module including a carrier and a conductive circuit film layer. The conductive circuit film layer is disposed on the carrier. The conductive circuit film layer has at least one conductive circuit structure including a vertical wire part and at least four horizontal wire parts. The vertical wire part extends along a thickness direction of the conductive circuit film layer. The at least four horizontal wire parts are connected to one another via the vertical wire part and extend along a direction substantially perpendicular to the vertical wire part. The at least four horizontal wire parts are symmetrically arranged or asymmetrically arranged with respect to the vertical wire part.

公开(公告)号：US20220005754A1

公开(公告)日：2022-01-06

申请号：US17031486

申请日：2020-09-24

申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

发明人： Ren-Shin CHENG ,  Shih-Hsien WU ,  Yu-Wei HUANG ,  Chih Ming SHEN ,  Yi-Chieh TSAI

IPC分类号： H01L23/495 ,  H01L23/498

摘要： A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.

公开(公告)号：US20210257279A1

公开(公告)日：2021-08-19

申请号：US17141035

申请日：2021-01-04

申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

发明人： Sheng-Che HUNG ,  Shih-Hsien WU ,  Yu-Wei HUANG

IPC分类号： H01L23/485 ,  H05K1/11 ,  H05K3/30 ,  H05K3/42

摘要： An electronic device having a substrate includes a substrate and at least one outer layer. The substrate has a plurality of first vias. The outer layer has a plurality of second vias. The outer layer is disposed on a side of the substrate. The first vias have a larger distribution density or quantity than the second vias so that a portion of the first vias are electrically connected to the second vias, and a portion of the first vias are electrically floating.

公开(公告)号：US20180183127A1

公开(公告)日：2018-06-28

申请号：US15468796

申请日：2017-03-24

申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

发明人： Yu-Wei HUANG ,  Shih-Hsien WU ,  Wei-Chung LO

IPC分类号： H01P3/12

CPC分类号： H01P3/121

摘要： An electromagnetic wave transmission board comprises a substrate. The substrate comprises a first dielectric layer and a second dielectric layer, and the first dielectric layer is stacked on the second dielectric layer. The first dielectric layer and the second dielectric layer together form a wave guiding space. The wave guiding space is configured for transmitting electromagnetic wave.

公开(公告)号：US20230187372A1

公开(公告)日：2023-06-15

申请号：US17886333

申请日：2022-08-11

申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

发明人： Tsung-Yi HUNG ,  Yu-Wei HUANG

IPC分类号： H01L23/544 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/544 ,  H01L24/20 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/1413 ,  H01L24/14 ,  H01L2224/2105 ,  H01L2224/2205 ,  H01L2223/54426 ,  H01L2224/05555 ,  H01L2224/0613

摘要： An electronic device includes a via-array substrate, an outer layer, and an alignment substrate. The via-array substrate has a plurality of first vias. The outer layer has a plurality of second vias and is disposed on a side of the via-array substrate. The first vias are greater in distribution density or quantity than the second vias. A part of the first vias is electrically connected to the second vias, and another part of the first vias is electrically floating. The alignment substrate includes a core layer disposed on the outer layer, a plurality of conductive traces, a plurality of interconnecting pads, and a plurality of alignment mark pads. The conductive traces are disposed in the core layer. The interconnecting pads and the alignment mark pads are disposed on a surface of the core layer located away from the outer layer. A part of the conductive traces electrically connects a part of the interconnecting pads and a part of the first vias. A pattern of each of the alignment mark pads is different from a pattern of each of the interconnecting pads.

公开(公告)号：US20240222305A1

公开(公告)日：2024-07-04

申请号：US18166517

申请日：2023-02-09

申请人： Industrial Technology Research Institute

发明人： Yu-Wei HUANG

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/24 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/16225 ,  H01L2224/16501 ,  H01L2224/24227 ,  H01L2224/73209 ,  H01L2924/1517

摘要： A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a circuit layer, and a plurality of contacts electrically connecting the circuit layer to the carrier. Each contact includes a metal portion and an insulating portion. The insulating portion surrounds the metal portion. A gap is formed between the contacts.