公开(公告)号：US10157859B2

公开(公告)日：2018-12-18

申请号：US15867080

申请日：2018-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shou-Zen Chang ,  Chi-Ming Huang ,  Kai-Chiang Wu ,  Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Han-Ping Pu ,  Albert Wan

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device. The semiconductor device structure includes a second conductive shielding layer under the first device. The first device is between the first conductive shielding layer and the second conductive shielding layer, and the second conductive shielding layer has a plurality of second openings.

公开(公告)号：US09899982B2

公开(公告)日：2018-02-20

申请号：US14948477

申请日：2015-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Hsien Tsai ,  Chien-Min Lin ,  Fu-Lung Hsueh ,  Han-Ping Pu ,  Sa-Lly Liu ,  Sen-Kuei Hsu

IPC: H01L29/93 ,  H01L23/528 ,  H01L23/522 ,  H03H1/00 ,  H03H7/01

CPC classification number: H03H1/0007 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5286 ,  H01L29/93 ,  H03H7/0115

Abstract: An integrated circuit (IC) die for electromagnetic band gap (EBG) noise suppression is provided. A power mesh and a ground mesh are stacked within a back end of line (BEOL) region overlying a semiconductor substrate, and an inductor is arranged over the power and ground meshes. The inductor comprises a plurality of inductor segments stacked upon one another and connected end to end to define a length of the inductor. A capacitor underlies the power and ground meshes, and is connected in series with the inductor. Respective terminals of the capacitor and the inductor are respectively coupled to the power and ground meshes. A method for manufacturing the IC die is also provided.

公开(公告)号：US09875972B1

公开(公告)日：2018-01-23

申请号：US15210067

申请日：2016-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shou-Zen Chang ,  Chi-Ming Huang ,  Kai-Chiang Wu ,  Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Han-Ping Pu ,  Albert Wan

IPC: H01L23/552 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/5382 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06555

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device.

公开(公告)号：US12062622B2

公开(公告)日：2024-08-13

申请号：US17883568

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Ping Pu ,  Hsiao-Wen Lee

IPC: H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US20240136280A1

公开(公告)日：2024-04-25

申请号：US18401815

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC: H01L23/525 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L23/552

CPC classification number: H01L23/525 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/5225 ,  H01L23/5329 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L23/5286 ,  H01L24/13

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

公开(公告)号：US11551999B2

公开(公告)日：2023-01-10

申请号：US16897300

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lipu Kris Chuang ,  Chung-Shi Liu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Ming-Kai Liu ,  Ting-Chu Ko

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367

Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

公开(公告)号：US11417616B2

公开(公告)日：2022-08-16

申请号：US16924116

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.

公开(公告)号：US11335666B2

公开(公告)日：2022-05-17

申请号：US16924192

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L25/00

Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

公开(公告)号：US11282810B2

公开(公告)日：2022-03-22

申请号：US16923115

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683 ,  H01L23/544

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US11244896B2

公开(公告)日：2022-02-08

申请号：US16258652

申请日：2019-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Chien Hsiao ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chieh-Yen Chen

IPC: H01L23/522 ,  H01L29/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L29/739 ,  H01L23/66 ,  H01L21/56 ,  H01L21/683

Abstract: A package structure includes a die, an encapsulant, and a first redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes a ground plane within the die. The encapsulant encapsulates the die. The first redistribution structure is over the active surface of the die. The first redistribution structure includes an antenna pattern electrically coupled with the ground plane. The antenna pattern is electrically connected to the die.