公开(公告)号：US20220013494A1

公开(公告)日：2022-01-13

申请号：US16924192

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L25/00

Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

公开(公告)号：US11127708B2

公开(公告)日：2021-09-21

申请号：US16676439

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Kai Liu ,  Han-Ping Pu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/538

Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.

公开(公告)号：US10978782B2

公开(公告)日：2021-04-13

申请号：US16858743

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Ping Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Albert Wan ,  Yu-Sheng Hsieh

IPC: H01L23/31 ,  H01Q1/38 ,  H01L23/66 ,  H01Q1/22 ,  H01Q21/06 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01Q9/04 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.

公开(公告)号：US20200075526A1

公开(公告)日：2020-03-05

申请号：US16676439

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Kai Liu ,  Han-Ping Pu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/538

Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.

公开(公告)号：US20190096841A1

公开(公告)日：2019-03-28

申请号：US15717974

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Kai Liu ,  Han-Ping Pu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/538

Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.

公开(公告)号：US11004809B2

公开(公告)日：2021-05-11

申请号：US16426365

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Ping Chiang ,  Yi-Che Chiang ,  Nien-Fang Wu ,  Min-Chien Hsiao ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683 ,  H01Q9/04 ,  H01Q21/06 ,  H01Q21/00 ,  H01L21/56 ,  H01L23/538 ,  H01Q1/22 ,  H01Q21/22

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

公开(公告)号：US20200020628A1

公开(公告)日：2020-01-16

申请号：US16035723

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

公开(公告)号：US11335666B2

公开(公告)日：2022-05-17

申请号：US16924192

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L25/00

Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

公开(公告)号：US11075159B2

公开(公告)日：2021-07-27

申请号：US16035723

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/532 ,  H01L21/768

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

公开(公告)号：US10312203B2

公开(公告)日：2019-06-04

申请号：US15625678

申请日：2017-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Yung-Ping Chiang ,  Nien-Fang Wu ,  Min-Chien Hsiao ,  Yi-Che Chiang ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.