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    Simplified Carrier Removable by Reduced Number of CMP Processes
    2.
    发明申请
    Simplified Carrier Removable by Reduced Number of CMP Processes 有权

    公开(公告)号：US20220395953A1

    公开(公告)日：2022-12-15

    申请号：US17455116

    申请日：2021-11-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Wei Chang ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Ting-Chu Ko

    IPC: B24B7/22 ,  B24B37/04 ,  B24B37/08 ,  B24B49/12

    Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.

    Semiconductor Packages and Methods of Forming the Same
    6.
    发明公开
    Semiconductor Packages and Methods of Forming the Same 审中-公开

    公开(公告)号：US20240332176A1

    公开(公告)日：2024-10-03

    申请号：US18192521

    申请日：2023-03-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ching-Yu Huang ,  Ting-Chu Ko

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L27/088

    CPC classification number: H01L23/5283 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/09 ,  H01L27/088 ,  H01L2224/0603 ,  H01L2224/06051

    Abstract: A method includes attaching a front-side of a first die to a wafer, the first bond pad being along a back-side of the first die, the wafer comprising a substrate and a transistor along the substrate, the transistor facing the wafer, the first die comprising: a first bond pad; a first back-side interconnect structure; a first front-side interconnect structure; a first semiconductor substrate interposed between the first back-side interconnect structure and the first front-side interconnect structure; and a first transistor along the first semiconductor substrate, the first transistor facing the front-side of the first die; forming a second bond pad over the first front-side interconnect structure; and attaching a second front-side of a second die to the second bond pad of the first die, the second die comprising a second semiconductor substrate and a second transistor, the second transistor facing the front-side of the second die.

    Memory device and manufacturing method thereof
    8.
    发明授权
    Memory device and manufacturing method thereof 有权

    公开(公告)号：US11335666B2

    公开(公告)日：2022-05-17

    申请号：US16924192

    申请日：2020-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ching-Yu Huang ,  Han-Ping Pu ,  Ming-Kai Liu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/373 ,  H01L25/00

    Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

    SIMPLIFIED CARRIER REMOVABLE BY REDUCED NUMBER OF CMP PROCESSES
    10.
    发明申请
    SIMPLIFIED CARRIER REMOVABLE BY REDUCED NUMBER OF CMP PROCESSES 有权

    公开(公告)号：US20240375236A1

    公开(公告)日：2024-11-14

    申请号：US18783920

    申请日：2024-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Wei Chang ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Ting-Chu Ko

    IPC: B24B7/22 ,  B24B37/04 ,  B24B37/08 ,  B24B49/12

    Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.

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