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21 条记录 (耗时 0.02 秒)

    Memory device and manufacturing method thereof
    7.
    发明授权
    Memory device and manufacturing method thereof 有权

    公开(公告)号：US11551999B2

    公开(公告)日：2023-01-10

    申请号：US16897300

    申请日：2020-06-10

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Lipu Kris Chuang ,  Chung-Shi Liu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Ming-Kai Liu ,  Ting-Chu Ko

    IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367

    摘要： A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

    Semiconductor device and semiconductor package
    9.
    发明授权
    Semiconductor device and semiconductor package 有权

    公开(公告)号：US10256203B2

    公开(公告)日：2019-04-09

    申请号：US15662261

    申请日：2017-07-27

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Lipu Kris Chuang ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Sen-Kuei Hsu

    IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/367 ,  H01L23/538

    摘要： A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

    SEMICONDCUTOR DEVICE AND SEMICONDCUTOR PACKAGE
    10.
    发明申请
    SEMICONDCUTOR DEVICE AND SEMICONDCUTOR PACKAGE 审中-公开

    公开(公告)号：US20190035752A1

    公开(公告)日：2019-01-31

    申请号：US15662261

    申请日：2017-07-27

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Lipu Kris Chuang ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Sen-Kuei Hsu

    IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/367 ,  H01L23/31

    摘要： A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.