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公开(公告)号：US11004786B2
公开(公告)日：2021-05-11
申请号：US16354173
申请日：2019-03-15
发明人： Chih-Hsuan Tai , Hao-Yi Tsai , Tsung-Hsien Chiang , Yu-Chih Huang , Chia-Hung Liu , Ban-Li Wu , Ying-Cheng Tseng , Po-Chun Lin
IPC分类号： H01L23/522 , H01L23/367 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/528 , H01L21/56 , H01L21/768
摘要： A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
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公开(公告)号：US20210118811A1
公开(公告)日：2021-04-22
申请号：US16655247
申请日：2019-10-17
发明人： Chun-Ti Lu , Hao-Yi Tsai , Ming-Hung Tseng , Tsung-Hsien Chiang , Yen-Liang Lin , Tzu-Sung Huang
摘要： A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.
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公开(公告)号：US20190371734A1
公开(公告)日：2019-12-05
申请号：US15992198
申请日：2018-05-30
发明人： Chih-Hao Chang , Hao-Yi Tsai , Tsung-Hsien Chiang , Tin-Hao Kuo
IPC分类号： H01L23/532 , H01L23/522 , H01L23/00 , H01L23/31 , H01L21/56
摘要： A package structure and a method of manufacturing the same are provided. The package structure includes a die, a RDL structure, an encapsulant and a conductive terminal. The die is on a redistribution layer (RDL) structure. The RDL structure comprises a polymer layer and a RDL in the polymer layer. The encapsulant is on the RDL structure and laterally aside the die. The encapsulant comprises a body part and an extending part underlying the body part. The conductive terminal is electrically connected to the RDL structure and the die. The body part of the encapsulant encapsulates sidewalls of the die. The extending part of the encapsulant extends into the polymer layer.
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公开(公告)号：US10157846B2
公开(公告)日：2018-12-18
申请号：US15292762
申请日：2016-10-13
IPC分类号： H01L21/44 , H01L23/538 , H01L21/48 , H01L23/00 , H01L21/683 , H01L21/56 , H01L25/065 , H01L23/31
摘要： Structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes cutting an upper portion of the dielectric layer to improve flatness of the dielectric layer. In addition, the method includes forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.
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公开(公告)号：US20230420331A1
公开(公告)日：2023-12-28
申请号：US17809039
申请日：2022-06-27
发明人： Ban-Li Wu , Tsung-Hsien Chiang , Tzu-Sung Huang , Chao-Hsien Huang , Chia-Lun Chang , Hsiu-Jen Lin , Ming Hung Tseng , Hao-Yi Tsai
IPC分类号： H01L23/367 , H01L25/16 , H01L23/498 , H01L21/48 , H01L23/373
CPC分类号： H01L23/3677 , H01L25/16 , H01L23/49822 , H01L23/49833 , H01L21/4857 , H01L21/486 , H01L23/3735 , H01L23/49838 , H01L24/16
摘要： A semiconductor package including one or more heat dissipation systems and a method of forming are provided. The semiconductor package may include one or more integrated circuit dies, an encapsulant surrounding the one or more integrated circuit dies, a redistribution structure over the one or more integrated circuit dies and the encapsulant. The redistribution structure may include one or more heat dissipation systems, which are electrically isolated from remaining portions of the redistribution structure. Each heat dissipation system may include a first metal pad, a second metal pad, and one or more metal vias connecting the first metal pad to the second metal pad.
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公开(公告)号：US20200294912A1
公开(公告)日：2020-09-17
申请号：US16354173
申请日：2019-03-15
发明人： Chih-Hsuan Tai , Hao-Yi Tsai , Tsung-Hsien Chiang , Yu-Chih Huang , Chia-Hung Liu , Ban-Li Wu , Ying-Cheng Tseng , Po-Chun Lin
IPC分类号： H01L23/522 , H01L23/00 , H01L23/31 , H01L23/367 , H01L23/48 , H01L23/528 , H01L21/56 , H01L21/768
摘要： A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
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公开(公告)号：US20200273806A1
公开(公告)日：2020-08-27
申请号：US16285216
申请日：2019-02-26
发明人： Tsung-Hsien Chiang , Hsien-Ming Tu , Hao-Yi Tsai , Tin-Hao Kuo
IPC分类号： H01L23/544 , H01L23/31 , H01L23/538 , H01L23/00 , H01L21/48 , H01L21/56 , B23K26/352
摘要： A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern. The front side redistribution structure is disposed on a front side of the encapsulated semiconductor device and electrically connected to the semiconductor device.
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公开(公告)号：US10700008B2
公开(公告)日：2020-06-30
申请号：US15992198
申请日：2018-05-30
发明人： Chih-Hao Chang , Hao-Yi Tsai , Tsung-Hsien Chiang , Tin-Hao Kuo
IPC分类号： H01L23/532 , H01L23/31 , H01L23/52 , H01L23/522 , H01L23/00 , H01L21/56
摘要： A package structure and a method of manufacturing the same are provided. The package structure includes a die, a RDL structure, an encapsulant and a conductive terminal. The die is on a redistribution layer (RDL) structure. The RDL structure comprises a polymer layer and a RDL in the polymer layer. The encapsulant is on the RDL structure and laterally aside the die. The encapsulant comprises a body part and an extending part underlying the body part. The conductive terminal is electrically connected to the RDL structure and the die. The body part of the encapsulant encapsulates sidewalls of the die. The extending part of the encapsulant extends into the polymer layer.
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公开(公告)号：US20230154764A1
公开(公告)日：2023-05-18
申请号：US17655645
申请日：2022-03-21
发明人： Tzu-Sung Huang , Tsung-Hsien Chiang , Ming Hung Tseng , Hao-Yi Tsai , Yu-Hsiang Hu , Chih-Wei Lin , Lipu Kris Chuang , Wei Lun Tsai , Kai-Ming Chiang , Ching Yao Lin , Chao-Wei Li , Ching-Hua Hsieh
IPC分类号： H01L21/48 , H01L23/498
CPC分类号： H01L21/4857 , H01L23/49822 , H01L23/49838 , H01L24/32
摘要： A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.
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公开(公告)号：US11107772B2
公开(公告)日：2021-08-31
申请号：US16285216
申请日：2019-02-26
发明人： Tsung-Hsien Chiang , Hsien-Ming Tu , Hao-Yi Tsai , Tin-Hao Kuo
IPC分类号： H01L23/544 , H01L23/538 , H01L23/00 , H01L21/48 , H01L21/56 , B23K26/352 , H01L23/31 , B23K101/40
摘要： A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern. The front side redistribution structure is disposed on a front side of the encapsulated semiconductor device and electrically connected to the semiconductor device.
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